Conductive pads forming method

• US 9,735,119 B1
• Filed: 07/25/2016
• Issued: 08/15/2017
• Est. Priority Date: 07/25/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Tzung-Han
• Primary Examiner(s): Sullivan, Caleen
• Application Number:
  US15/219,265
• Time in Patent Office: 386 Days
• Field of Search: 257751, 438612
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

In some embodiments, the present disclosure provides a conductive pads forming method. The conductive pads forming method may include providing a contact pad or a test pad electrically connected to a semiconductor component; and forming the conductive pads electrically connected to the contact pad or the test pad through the conductive routes, respectively.

Claims

1. A conductive pads forming method comprising:

providing a contact pad electrically connected to a semiconductor component;

forming a plurality of conductive pads connected to the contact pad respectively; and

bonding a plurality of metal wires to the conductive pads, respectively.

2. The conductive pads forming method of claim 1, wherein the forming of the conductive pads comprises:

forming a plurality of conductive routes electrically connected to each other; and

forming the conductive pads electrically connected to the contact pad through the conductive routes, respectively.

3. The conductive pads forming method of claim 1, wherein the forming of the conductive pads comprises:

forming a plurality of conductive routes insulated with each other above the contact pad; and

forming the conductive pads electrically connected to the contact pad through the conductive routes, respectively.

4. The conductive pads forming method of claim 1, wherein the bonding of the metal wires comprises embedding the metal wires into the conductive pads.

5. The conductive pads forming method of claim 1, further comprising forming supporting layers on the contact pad, wherein the supporting layers comprise at least one interlayer, wherein the forming of the conductive pads comprises forming the conductive pads on the supporting layers, respectively.

6. The conductive pads forming method of claim 5, wherein the at least one interlayer of the supporting layers comprises silicon nitride.

7. A conductive pads forming method comprising:

providing a wafer comprising a test pad;

forming a plurality of conductive pads on the wafer, wherein each conductive pad is electrically connected to the test pad; and

bonding a plurality of metal wires to the conductive pads, respectively.

8. The conductive pads forming method of claim 7, wherein the forming of the conductive pads comprises tinning a plurality of conductive routes each electrically connected between a corresponding one of the conductive pads and the test pad.

9. The conductive pads forming method of claim 8, wherein the forming of the conductive routes comprises forming the conductive routes electrically connected to each other.

10. The conductive pads forming method of claim 8, wherein the forming of the conductive routes comprises forming the conductive routes insulated with each other above the test pad.

11. The conductive pads forming method of claim 7, further comprising:

forming a plurality of scribe lines on the wafer;

forming a via on the wafer between two adjacent scribe lines; and

forming the test pad inside the via.

12. The conductive pads forming method of claim 11, further comprising:

thinning the wafer, to form first regions and second regions, wherein the second regions are located between the first regions and the via, and second surfaces of the wafer on the second regions are lower compared to first surfaces of the wafer on the first regions; and

forming the conductive pads on the second regions.

13. The conductive pads forming method of claim 12, wherein the forming of the via and the thinning of the wafer are performed at the same time.

14. The conductive pads forming method of claim 12, wherein a surface of the conductive pads away from the wafer is substantially aligned with or lower than a surface of the wafer on the first regions.

15. The conductive pads forming method of claim 11, wherein the forming of the conductive pads comprises forming the conductive pads across the scribe lines.

16. The conductive pads forming method of claim 7, wherein the bonding of the metal wires comprises embedding the metal wires into the conductive pads.