Compound semiconductor transistor with gate overvoltage protection

• US 9,735,141 B2
• Filed: 02/23/2016
• Issued: 08/15/2017
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Vielemeyer, Martin, Hutzler, Michael, Curatola, Gilberto, Pozzovivo, Gianmauro
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US15/050,823
• Publication Number:
  US 20160247794A1
• Time in Patent Office: 539 Days
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Claims

1. A transistor device, comprising:

a compound semiconductor body;

a drain disposed in the compound semiconductor body;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device electrically connected between the source and the gate and comprising alternating regions of p-type and n-type silicon disposed in a first trench formed in the compound semiconductor body.

2. The transistor device of claim 1, wherein the compound semiconductor body comprises a doped silicon substrate or a doped compound semiconductor substrate, a first compound semiconductor material on the doped substrate and a second compound semiconductor material on the first compound semiconductor material, and wherein the first and second compound semiconductor materials have different had gaps and a two-dimensional charge carrier gas arises in the first compound semiconductor material and forms the channel region.

3. The transistor device of claim 2, wherein the first trench extends through the first and second compound semiconductor materials to the doped substrate, wherein the source is electrically connected to the doped substrate through a conductive via disposed in a second trench extending through the first and second compound semiconductor materials to the doped substrate, wherein the second trench is laterally spaced apart from the first trench, and wherein the alternating regions of p-type and n-type silicon disposed in the first trench are electrically insulated from the first and second compound semiconductor materials.

4. The transistor device of claim 3, wherein the doped substrate is an n-type doped Si substrate, an n-type silicon region of the gate overvoltage protection device is electrically connected to the gate, and a p-type silicon region of the gate overvoltage protection device contacts the n-type doped Si substrate.

5. The transistor device of claim 3, wherein the alternating regions of p-type and n-type silicon end prior to the doped substrate, and wherein the gate overvoltage protection device is connected at one end to the gate and to the doped substrate an opposing end through a conductive via disposed in the first trench between the alternating regions of p-type and n-type silicon and the doped substrate.

6. The transistor device of claim 3, further comprising a device isolation region adjacent the source, and wherein the gate overvoltage protection device is laterally spaced apart from the source by the device isolation region.

7. The transistor device of claim 3, wherein the gate overvoltage protection device comprises a first n-type silicon region disposed in the first trench and connected to the gate, a second n-type silicon region disposed in the first trench below the first n-type silicon region and connected to the source, and a p-type silicon region disposed in the first trench between the first and second n-type silicon regions, the transistor device further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate;

a source terminal connected to the doped substrate;

an additional terminal; and

a resistor or additional gate overvoltage protection device disposed in a third trench laterally spaced apart from the first and second trenches and extending through the first and second compound semiconductor materials to the doped substrate, the resistor or additional gate overvoltage protection device connected to the doped substrate at one end and to the additional terminal at an opposing end.

8. The transistor device of claim 2, wherein the gate overvoltage protection device comprises:

a first series of alternating regions of p-type and n-type silicon disposed in the first trench which extends through the first and second compound semiconductor materials to the doped substrate with the source connected to the doped substrate through the first series of alternating p-type and n-type silicon regions, the first series of alternating p-type and n-type silicon regions being electrically insulated from the first and second compound semiconductor materials; and

a second series of alternating regions of p-type and n-type silicon disposed in a second trench laterally spaced apart from the first trench and extending through the first and second compound semiconductor materials to the doped substrate with the gate connected to the doped substrate through the second series of alternating p-type and n-type silicon regions, the second series of alternating p-type and n-type silicon regions being electrically insulated from the first and second compound semiconductor materials.

9. The transistor device of claim 8, further comprising a device isolation region adjacent the source, wherein the source contacts the channel region at one side and is spaced apart from the second series of alternating p-type and n-type silicon regions by the device isolation region at a second side different than the first side, and wherein the first trench extends from the source to the doped substrate so that the first series of alternating p-type and n-type silicon regions is disposed under the source.

10. The transistor device of claim 8, wherein the gate overvoltage protection device is disposed in an inactive region of the transistor device, the source and gate extend from an active region of the transistor device to the inactive region, the first series of alternating p-type and n-type silicon regions connects the source to the doped substrate in the inactive region, and the second series of alternating p-type and n-type silicon regions connects the gate to the doped substrate in the inactive region.

11. The transistor device of claim 8, further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate;

a source terminal connected to the doped substrate; and

an additional terminal connected to the doped substrate.

12. The transistor device of claim 8, wherein the first series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction, and wherein the second series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction.

13. A transistor device, comprising:

a compound semiconductor body comprising a doped substrate, a first compound semiconductor material on the doped substrate and a second compound semiconductor material on the first compound semiconductor material;

a drain disposed in the compound semiconductor body;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device electrically connected between the source and the gate and comprising alternating regions of p-type and n-type silicon disposed on a dielectric material formed on the second compound semiconductor material,

wherein one of the p-type or n-type silicon regions is electrically connected to the gate and a different one of the p-type or n-type silicon regions is electrically connected to the source through a first conductive via disposed in a first trench extending through the dielectric material to the source.

14. The transistor device of claim 13, wherein the source is electrically connected to the doped substrate through a second conductive via disposed in a second trench extending through the first and second compound semiconductor materials to the doped substrate.

15. The transistor device of claim 13, wherein the gate overvoltage protection device comprises a first n-type silicon region on the dielectric material and connected to the gate, a second n-type silicon region on the dielectric material and connected to the source, a third n-type silicon region on the dielectric material, a first p-type silicon region on the dielectric material and separating the first and second n-type silicon regions, and a second p-type silicon region on the dielectric material and separating the second and third n-type silicon regions, the transistor device further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate and the first n-type silicon region;

a source terminal connected to the source and the second n-type silicon region; and

an additional terminal connected to the third n-type silicon region.

16. A transistor device, comprising:

a compound semiconductor body comprising a doped substrate, a first compound semiconductor material on the doped substrate and a second compound semiconductor material on the first compound semiconductor material;

a drain disposed in the compound semiconductor body;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device electrically connected between the source and the gate and comprising;

a first series of alternating regions of p-type and n-type silicon disposed in a first trench which extends through the first and second compound semiconductor materials to the doped substrate, the source being connected to the doped substrate through the first series of alternating p-type and n-type silicon regions; and

a second series of alternating regions of p-type and n-type silicon disposed in a second trench laterally spaced apart from the first trench and extending through the first and second compound semiconductor materials to the doped substrate, the gate being connected to the doped substrate through the second series of alternating p-type and n-type silicon regions.

17. The transistor device of claim 16, further comprising a device isolation region adjacent the source, wherein the source contacts the channel region at one side and is spaced apart from the second series of alternating p-type and n-type silicon regions by the device isolation region at a second side different than the first side, and wherein the first trench extends from the source to the doped substrate so that the first series of alternating p-type and n-type silicon regions is disposed under the source.

18. The transistor device of claim 16, wherein the gate overvoltage protection device is disposed in an inactive region of the transistor device, the source and gate extend from an active region of the transistor device to the inactive region, the first series of alternating p-type and n-type silicon regions connects the source to the doped substrate in the inactive region, and the second series of alternating p-type and n-type silicon regions connects the gate to the doped substrate in the inactive region.

19. The transistor device of claim 16, further comprising:

a drain terminal connected to the drain;

a gate terminal connected to the gate;

a source terminal connected to the doped substrate; and

an additional terminal connected to the doped substrate.

20. The transistor device of claim 16, wherein the first series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction, and wherein the second series of alternating regions of p-type and n-type silicon comprises at least one pnp or npn junction.

21. A transistor device, comprising:

a compound semiconductor body comprising an n-type doped substrate, a first compound semiconductor material on the n-type doped substrate and a second compound semiconductor material on the first compound semiconductor material;

a drain disposed in the compound semiconductor body;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device electrically connected between the source and the gate and comprising;

a first trench extending from the source to the n-type doped substrate and filled with a p-type silicon-containing semiconductor material;

a second trench spaced apart from the first trench and extending through the first and second compound semiconductor materials to the n-type doped substrate, the second trench filled with a p-type silicon-containing semiconductor material; and

a region of the n-type doped substrate disposed between the first and second trenches.

22. A transistor device, comprising:

a compound semiconductor body comprising a doped substrate and at least one epitaxial layer on the doped substrate;

a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region;

a gate operable to control the channel region; and

a gate overvoltage protection device electrically connected between the source and the gate and comprising;

a first trench extending from the source to the doped substrate and filled with a doped silicon-containing semiconductor material of the same doping type as the doped substrate;

a second trench spaced apart from the first trench and extending through the at least one epitaxial layer to the doped substrate, the second trench filled with a doped silicon-containing semiconductor material of the same doping type as the doped substrate; and

an implanted region formed in the doped substrate underneath and in contact with at least one of the first and second filled trenches, the implanted region having the opposite doping type as the doped substrate.

23. The transistor device of claim 22, wherein the implanted region is underneath and in contact with both filled trenches and continuous in the doped substrate between the first and second trenches.