Semiconductor carrier with vertical power FET module

• US 9,735,148 B2
• Filed: 06/09/2014
• Issued: 08/15/2017
• Est. Priority Date: 02/19/2002
• Status: Active Grant

• Current Assignee: L. Pierre De Rochemont
• Original Assignee: L. Pierre De Rochemont
• Inventors: de Rochemont, L. Pierre
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US14/299,018
• Publication Number:
  US 20150061759A1
• Time in Patent Office: 1,163 Days
• Field of Search: 257724, 257300, 257 14, 257254, 257296, 257330, 361 17, 343873
• CPC Class Codes: H01F 17/06 with core substantially closed in itself, e.g. toroid
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 30/16 Toroidal transformers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 3/28 using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
• CPC Class Codes: Y10T 428/12493 Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]

Abstract

A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.

Claims

1. A circuit module having a semiconductor power switch, comprising:

a planar first electrode;

a first layer of doped semiconductor material disposed on the planar first electrode that forms ohmic contact with the planar first electrode;

a second layer of doped semiconductor material disposed on the first layer that is electronically patterned to form a field effect transistor (FET);

a second electrode disposed upon the second layer;

an elongated gate electrode located to modulate current flow from the planar first electrode through the second layer to the second electrode and having a ratio of gate electrode width to gate electrode length that is greater than or equal to 100;

wherein the elongated gate electrode forms a serpentine pattern over the second layer and is insulated from the second layer and the second electrode; and

wherein the elongated gate electrode comprises a conductor that forms a resonant transmission line by configuring the conductor to form the serpentine patterned elongated gate electrode that contains a capacitive element determined by charge collected beneath the elongated gate electrode, a resistive element determined by the conductor length and cross-sectional area of the conductor used to form the serpentine patterned elongated gate , and an inductive element formed by half-turns that loop the serpentine pattern back upon itself, which resonant transmission line is resonant at a frequency determined by internal capacitance and inductance.

2. The switch of claim 1, wherein the elongated gate electrode is meandered adjacent to a contiguous surface area of the second layer to maximize gate electrode width over that contiguous surface area.

3. The switch of claim 2, wherein the first layer is formed as a region of the substrate and the contiguous surface area is surrounded by a toroidal transformer having a ceramic core formed on the substrate.

4. The switch of claim 2, wherein the elongated gate electrode includes adjacent parallel gate portions.

5. The switch of claim 1, wherein the FET includes a pair of parallel elongated channel regions located beneath the elongated gate electrode.

6. The switch of claim 5, wherein the elongated gate electrode is meandered and has a gate electrode width to gate electrode length ratio that is greater than or equal to 10⁶.

7. The switch of claim 1, wherein the first semiconductor layer is doped to form a power FET as an insulated gate bipolar transistor when making electrical contact with the second semiconductor layer.