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Semiconductor device and manufacturing method thereof

  • US 9,735,150 B2
  • Filed: 06/06/2016
  • Issued: 08/15/2017
  • Est. Priority Date: 07/30/2015
  • Status: Active Grant
First Claim
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1. A semiconductor device including a diode,the semiconductor device comprising a silicon substrate, trench insulating films, trench electrodes, an interlayer insulating film, contact plugs, an upper electrode layer, a protective insulating film, and a lower electrode layer,whereinthe silicon substrate is configured so that:

  • the silicon substrate comprises an element field and an external field, a plurality of trenches extending in a striped pattern being provided in an upper surface of the silicon substrate in the element field, and the external field being adjacent to the element field in a longitudinal direction of the trenches;

    the silicon substrate comprises a plurality of inter-trench ranges, each of the inter-trench ranges being provided in each of positions between the two neighboring trenches in a plan view of the upper surface of the silicon substrate;

    a plurality of specific inter-trench ranges is selected from among the plurality of the inter-trench ranges;

    each of the specific inter-trench ranges comprises an anode region, a barrier region and a pillar region;

    each of the anode regions is a p-type semiconductor region exposed on the upper surface of the silicon substrate;

    each of the barrier regions is an n-type semiconductor region located under the anode region;

    each of the pillar regions is an n-type semiconductor region extending from a position exposed on the upper surface of the silicon substrate to a position being in contact with the barrier region;

    the silicon substrate comprises a drift region and a cathode region located on a lower side with respect to the barrier regions;

    the drift region is located under the barrier regions, connected to the barrier regions directly or via a p-type semiconductor region, and having an impurity concentration lower than an impurity concentration of the barrier regions; and

    the cathode region is an n-type semiconductor region located under the drift region, exposed on a lower surface of the silicon substrate, and having an impurity concentration higher than the impurity concentration of the drift region,each of the trench insulating films covers an inner surface of the corresponding trench,each of the trench electrodes is located in the corresponding trench of which inner surface is covered by the trench insulating film,the interlayer insulating film covers the upper surface of the silicon substrate in the element filed and upper surfaces of the trench electrodes,a first contact hole and a second contact hole penetrating the interlayer insulating film are provided in each of the specific inter-trench ranges,each of the second contact holes is located in a position closer to the external field than the corresponding first contact hole,each of the second contact holes has a width narrower than a width of the corresponding first contact hole,each of the contact plugs is located in the corresponding second contact hole,the contact plug comprises a first metal layer being in contact with the upper surface of the silicon substrate and a second metal layer located on the first metal layer,the upper electrode layer covers an upper surface of the interlayer insulating film, upper surfaces of the second metal layers, and inner surfaces of the first contact holes,the upper electrode layer has a thickness greater than a thickness of the first metal layers,the protective insulating film covers an upper surface of the external field and a part of the upper electrode layer,the protective insulating film comprises an end portion extending on the upper electrode layer through a range located above the plurality of the second contact holes along a direction intersecting with the plurality of trenches,the lower electrode layer covers the lower surface of the silicon substrate,each of the anode regions is in contact with the corresponding first metal layer by ohmic contact,the pillar regions are in contact with the upper electrode layer by Schottky contact and not in contact with the first metal layer, andthe cathode region is in contact with the lower electrode layer.

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