Semiconductor device and manufacturing method thereof

• US 9,735,150 B2
• Filed: 06/06/2016
• Issued: 08/15/2017
• Est. Priority Date: 07/30/2015
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Yakushigawa, Yuki, Iwasaki, Shinya, Kameyama, Satoru
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): INOUSSA, MOULOUCOULAY
• Application Number:
  US15/174,337
• Publication Number:
  US 20170033099A1
• Time in Patent Office: 435 Days
• Field of Search: 257140, 257155, 257498, 257328, 438270, 438272, 438268, 438237, 438329
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.

Claims

1. A semiconductor device including a diode,

the semiconductor device comprising a silicon substrate, trench insulating films, trench electrodes, an interlayer insulating film, contact plugs, an upper electrode layer, a protective insulating film, and a lower electrode layer,

wherein

the silicon substrate is configured so that:

the silicon substrate comprises an element field and an external field, a plurality of trenches extending in a striped pattern being provided in an upper surface of the silicon substrate in the element field, and the external field being adjacent to the element field in a longitudinal direction of the trenches;

the silicon substrate comprises a plurality of inter-trench ranges, each of the inter-trench ranges being provided in each of positions between the two neighboring trenches in a plan view of the upper surface of the silicon substrate;

a plurality of specific inter-trench ranges is selected from among the plurality of the inter-trench ranges;

each of the specific inter-trench ranges comprises an anode region, a barrier region and a pillar region;

each of the anode regions is a p-type semiconductor region exposed on the upper surface of the silicon substrate;

each of the barrier regions is an n-type semiconductor region located under the anode region;

each of the pillar regions is an n-type semiconductor region extending from a position exposed on the upper surface of the silicon substrate to a position being in contact with the barrier region;

the silicon substrate comprises a drift region and a cathode region located on a lower side with respect to the barrier regions;

the drift region is located under the barrier regions, connected to the barrier regions directly or via a p-type semiconductor region, and having an impurity concentration lower than an impurity concentration of the barrier regions; and

the cathode region is an n-type semiconductor region located under the drift region, exposed on a lower surface of the silicon substrate, and having an impurity concentration higher than the impurity concentration of the drift region,

each of the trench insulating films covers an inner surface of the corresponding trench,

each of the trench electrodes is located in the corresponding trench of which inner surface is covered by the trench insulating film,

the interlayer insulating film covers the upper surface of the silicon substrate in the element filed and upper surfaces of the trench electrodes,

a first contact hole and a second contact hole penetrating the interlayer insulating film are provided in each of the specific inter-trench ranges,

each of the second contact holes is located in a position closer to the external field than the corresponding first contact hole,

each of the second contact holes has a width narrower than a width of the corresponding first contact hole,

each of the contact plugs is located in the corresponding second contact hole,

the contact plug comprises a first metal layer being in contact with the upper surface of the silicon substrate and a second metal layer located on the first metal layer,

the upper electrode layer covers an upper surface of the interlayer insulating film, upper surfaces of the second metal layers, and inner surfaces of the first contact holes,

the upper electrode layer has a thickness greater than a thickness of the first metal layers,

the protective insulating film covers an upper surface of the external field and a part of the upper electrode layer,

the protective insulating film comprises an end portion extending on the upper electrode layer through a range located above the plurality of the second contact holes along a direction intersecting with the plurality of trenches,

the lower electrode layer covers the lower surface of the silicon substrate,

each of the anode regions is in contact with the corresponding first metal layer by ohmic contact,

the pillar regions are in contact with the upper electrode layer by Schottky contact and not in contact with the first metal layer, and

the cathode region is in contact with the lower electrode layer.

2. The semiconductor device of claim 1, further comprising a surface electrode layer covering an upper surface of the upper electrode layer in a range not covered by the protective insulating film, the surface electrode layer further covering a part of the protective insulating film and configured of a metal different in kind from the upper electrode layer.

3. A method for manufacturing a semiconductor device including a diode, the method comprising:

preparing a silicon substrate configured so that;

the silicon substrate comprises an element field and an external field, a plurality of trenches extending in a striped pattern being provided in an upper surface of the silicon substrate in the element field, and the external field being adjacent to the element field in a longitudinal direction of the trenches,

each of the trench insulating films covers an inner surface of corresponding trench,

each of the trench electrodes is located in the corresponding trench of which inner surface is covered by the trench insulating film,

the silicon substrate comprises a plurality of inter-trench ranges, each of the inter-trench ranges being provided in each of positions between the two neighboring trenches in a plan view of the upper surface of the silicon substrate,

a plurality of specific inter-trench ranges is selected from among the plurality of the inter-trench ranges;

each of the specific inter-trench ranges comprises an anode region, a barrier region and a pillar region,

each of the anode regions is a p-type semiconductor region exposed on the upper surface of the silicon substrate,

each of the barrier regions is an n-type semiconductor region located under the anode region,

each of the pillar regions is an n-type semiconductor region extending from a position exposed on the upper surface of the silicon substrate to a position being in contact with the barrier region, and

the silicon substrate comprises a drift region located under the barrier regions, connected to the barrier regions directly or via a p-type semiconductor region, and having an impurity concentration lower than an impurity concentration of the barrier regions;

forming an interlayer insulating film covering the upper surface of the silicon substrate in the element filed and upper surfaces of the trench electrodes;

forming first contact holes and second contact holes penetrating the interlayer insulating film in each of the specific inter-trench ranges, each of the second contact holes being located in a position closer to the external field than the corresponding first contact hole, and each of the second contact holes having a width narrower than a width of the corresponding first contact hole, each of the pillar regions exposed on a bottom surface of the corresponding first contact hole, each of the anode regions exposed on a bottom surface of the corresponding second contact hole, and the pillar regions not exposed on the bottom surfaces of the second contact holes;

forming a first metal layer being in contact with the corresponding anode region by ohmic contact on the bottom surface of the corresponding second contact hole;

forming a second metal layer on the corresponding first metal layer by after the formation of the first metal layers;

forming an upper electrode layer on an upper surface of the interlayer insulating film, upper surfaces of the second metal layers, and inner surfaces of the first contact holes after the formation of the second contact holes, the upper electrode layer having a thickness greater than a thickness of the first metal layers, and the upper electrode layer being in contact with the pillar regions by Schottky contact in the first contact holes;

forming a protective insulating film covering an upper surface of the external field and a part of the upper electrode layer, the protective insulating film comprising an end portion extending on the upper electrode layer through a range located above the plurality of the second contact holes along a direction intersecting with the plurality of trenches;

forming an n-type cathode region located under the drift region, exposed on a lower surface of the silicon substrate, and having an impurity concentration higher than an impurity concentration of the drift region; and

forming a lower electrode layer being in contact with the cathode region on the lower surface of the silicon substrate.

4. The method of claim 3, wherein the formation of the second metal layers comprises:

depositing a material layer of the second metal layers on the upper surface of the interlayer insulating film, the inner surface of the corresponding first contact hole, and the inner surface of the corresponding second contact hole, the material layer having a thickness greater than half of the width of the second contact holes and smaller than half of the width of the first contact holes; and

etching the first metal layers and the material layer so that an upper surface of the interlayer insulating film is exposed, bottom surfaces of the first contact holes are exposed, and the first metal layers and the second metal layers remain in a state in which each of the first metal layers and the second metal layers covers the bottom surface of the corresponding second contact hole.

5. The method of claim 3, further comprising:

forming a surface electrode layer covering an upper surface of the upper electrode layer in a range not covered by the protective insulating film, the surface electrode layer further covering a part of the protective insulating film and configured of a metal different in kind from the upper electrode layer.