Active area designs for silicon carbide super-junction power devices
First Claim
1. A silicon carbide (SiC) super-junction (SJ) device, comprising:
- an active area including one or more charge balance (CB) layers, wherein each CB layer comprises;
a semiconductor layer having a first conductivity-type; and
a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer, wherein the plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device, wherein a doping concentration of the plurality of floating regions is between 2×
1016 cm−
3 and 1×
1018 cm−
3, and wherein a spacing between the plurality of floating regions of a particular CB layer of the one or more CB layers is greater than or equal to 10% of a thickness of the particular CB layer and is less than or equal to the thickness of the particular CB layer.
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Accused Products
Abstract
The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.
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Citations
18 Claims
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1. A silicon carbide (SiC) super-junction (SJ) device, comprising:
an active area including one or more charge balance (CB) layers, wherein each CB layer comprises; a semiconductor layer having a first conductivity-type; and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer, wherein the plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device, wherein a doping concentration of the plurality of floating regions is between 2×
1016 cm−
3 and 1×
1018 cm−
3, and wherein a spacing between the plurality of floating regions of a particular CB layer of the one or more CB layers is greater than or equal to 10% of a thickness of the particular CB layer and is less than or equal to the thickness of the particular CB layer.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of manufacturing a silicon carbide (SiC) super-junction (SJ) device, comprising:
fabricating a first charge balance (CB) layer, comprising; forming a first semiconductor layer having a first conductivity-type on top of a SiC substrate layer; and implanting a first plurality of floating regions having a second conductivity-type into the first semiconductor layer, wherein a doping concentration of the first plurality of floating regions is between approximately 2×
1016 cm−
3 and approximately 1×
1018 cm−
3, and wherein a spacing between the first plurality of floating regions is greater than or equal to 10% of a thickness of the first semiconductor layer and less than or equal to the thickness of the first semiconductor layer.- View Dependent Claims (15, 16, 17, 18)
Specification