Trench-gate RESURF semiconductor device and manufacturing method

• US 9,735,254 B2
• Filed: 03/11/2015
• Issued: 08/15/2017
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Inventors: Rutter, Philip, Peake, Steven Thomas
• Primary Examiner(s): Cao, Phat X
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/644,272
• Publication Number:
  US 20150187913A1
• Time in Patent Office: 888 Days
• Field of Search: 438270
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Claims

1. A method of manufacturing a trench-gate semiconductor device, comprising:

forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region;

etching a gate trench into the substrate;

forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench;

implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant;

depositing, doping and annealing a gate electrode in the gate trench;

implanting and annealing a semiconductor body region on each side of the gate trench;

implanting and annealing source regions on each side of the gate trench over the semiconductor body region;

forming a second portion of gate oxide on top of the first portion of gate oxide;

etching the semiconductor body region using the second portion of gate oxide as a mask to form a moat region at the sides of the source regions to form contact openings for contact with the source regions;

implanting and annealing RESURF regions at a base of the moat, wherein the RESURF regions are formed on each side of the gate trench, doped with the second type of dopant of opposite polarity type to the first type of dopant, and extend more deeply into the drift region than the gate trench; and

depositing and patterning a metallisation layer to form source and gate contacts,

wherein the pillar region is beneath and in substantial contact with the gate trench and configured and arranged to act as an additional RESURF region and reduce the effective width of the drift region in an area between the RESURF regions and increase gate shielding, and

wherein the pillar region is formed to a depth which is at least substantially equal to the depth of the RESURF regions.

2. A method as claimed in claim 1, wherein the pillar region is formed with a width of between 0.7 and 1.0 times the width of the gate trench.

3. A method as claimed in claim 1, wherein the first type of dopant is n-type and the second type of dopant is p-type.

4. A method as claimed in claim 1, further comprising forming an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the RESURF regions.

5. A method as claimed in claim 1, further comprising depositing and patterning a metallisation layer on the opposite side of the substrate to the source and gate contacts to form a drain contact.

6. A method as claimed in claim 1, further comprising forming an implant region connected to the source regions and to the pillar region to bias the pillar region at a potential of the source regions.

7. A method as claimed in claim 1, further comprising forming the RESURF regions with a silicon layer doped with the first type of dopant, and wherein the RESURF regions are configured to interact with the device drift region to deplete electrons in the device drift region and reduce an electric field that occurs within the device drift region.

8. A method as claimed in claim 1, wherein the contact openings provide access to a lateral portion of the source regions.

9. The method of claim 1, wherein the implanting the pillar region beneath the gate trench includes the use of implant energies ranging from 120 keV to 260 keV and occurs after the formation of the thicker gate oxide at the bottom of the trench.

10. The method of claim 9, wherein the implanting the pillar region beneath the gate trench uses Boron.

11. A method of manufacturing a trench-gate semiconductor device, comprising:

forming a silicon substrate with an epitaxial layer doped with a first type of dopant, and which defines a device drift region;

etching a gate trench into the substrate;

forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench;

implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant;

depositing, doping and annealing a gate electrode in the gate trench;

implanting and annealing a semiconductor body region on each side of the gate trench;

implanting and annealing source regions on each side of the gate trench over the semiconductor body region;

forming a second portion of gate oxide on top of the first portion of gate oxide;

etching the semiconductor body region using the second portion of gate oxide as a mask to form a moat region at the sides of the source regions and contact openings for contact with the source regions;

implanting and annealing RESURF regions at a base of the moat;

depositing and patterning a metallisation layer to form source and gate contacts;

forming an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the implanted and annealed RESURF regions, wherein the implant region is connected to the source regions and to the pillar region to bias the pillar region at a potential of the source regions, and wherein the pillar region beneath the gate trench is configured and arranged relative to the implanted and annealed RESURF regions to act as an additional RESURF region and reduce the effective width of the drift region between the implanted and annealed RESURF regions and increasing gate shielding.

12. A method of manufacturing a trench-gate semiconductor device, comprising:

etching a gate trench into a silicon substrate having an epitaxial layer, the epitaxial layer being doped with a first type of dopant and defining a device drift region;

forming a first portion of a gate oxide against at least side walls of the trench and forming a thicker gate oxide at a bottom of the trench;

implanting a pillar region beneath the gate trench doped with a second type of dopant of opposite type to the first type of dopant;

forming a gate electrode in the gate trench, a semiconductor body region on each side of the gate trench, and source regions on each side of the gate trench over the semiconductor body region;

forming a second portion of gate oxide on top of the first portion of gate oxide,

a moat region at the sides of the source regions to form contact openings for contact with the source regions;

implanting and annealing RESURF regions at a base of the moat; and

forming a metallisation layer to form source and gate contacts, an implant region of the second type of dopant at ends of the gate trench to couple the pillar region to the RESURF regions, and causing the source regions to be connected to the pillar region in order to bias the pillar region at a potential of the source regions, wherein the pillar region implanted beneath the gate trench is configured and arranged with the RESURF regions to act as an additional RESURF region and reduce the effective width of the drift region and increase gate shielding.