Semiconductor device including a stacked wire structure

• US 9,735,274 B2
• Filed: 11/20/2015
• Issued: 08/15/2017
• Est. Priority Date: 11/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Wu, Cheng-Hsien, Yeh, Chih-Chieh
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US14/947,650
• Publication Number:
  US 20170148907A1
• Time in Patent Office: 634 Days
• Field of Search: 257368, 257407
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a stacked wire structure formed over the substrate. The semiconductor device structure also includes a gate structure formed over a middle portion of the stacked wire structure and a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure. The S/D structure includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

Claims

1. A semiconductor device structure, comprising:

a substrate;

a stacked wire structure formed over the substrate, wherein the stacked wire structure comprises a second semiconductor wire over a first semiconductor wire, and the first semiconductor wire and the second semiconductor wire are made of different materials;

a gate structure formed over a middle portion of the stacked wire structure; and

a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure, wherein the S/D structure comprises a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.

2. The semiconductor device structure as claimed in claim 1, wherein the substrate has (110) surface orientation or (111) surface orientation.

3. The semiconductor device structure as claimed in claim 1, further comprising:

a spacer formed between the gate structure and the S/D structure.

4. The semiconductor device structure as claimed in claim 1, wherein the S/D structure comprises a sidewall portion over sidewalls of the stacked wire structure and a top portion over the top surface of the stacked wire structure, wherein the sidewall portion has a first thickness along a horizontal direction, a top portion has a second thickness along a vertical direction, and the second thickness is greater than the first thickness.

5. The semiconductor device structure as claimed in claim 1, wherein the S/D structure comprises a first portion over sidewalls of the first semiconductor wire and a second portion over sidewalls of the second semiconductor wire, and the first portion is thicker than, or thinner than, the second portion.

6. The semiconductor device structure as claimed in claim 5, wherein the first portion and the second portion of the S/D structure have a periodical wave-like profile.

7. The semiconductor device structure as claimed in claim 5, wherein the first portion and the second portion of the S/D structure are oriented along <

112>

, <

111>

or <

100>

direction.

8. The semiconductor device structure as claimed in claim 1, further comprising:

an isolation structure formed over the substrate, wherein a bottom surface of the stacked wire structure is level with a top surface of the isolation structure.

9. The semiconductor device structure as claimed in claim 8, further comprising:

a fin structure extending above the substrate, wherein the fin structure is embedded in the isolation structure.

10. The semiconductor device structure as claimed in claim 1, further comprising:

a silicide layer formed over the S/D structure; and

a contact structure formed over the silicide layer.

11. The semiconductor device structure as claimed in claim 1, wherein a channel region is formed in the stacked wire structure and is covered by the gate structure, and the channel region is oriented along <

112>

, <

111>

or <

100>

direction.

12. A semiconductor device structure, comprising:

a substrate with (110) surface orientation or (111) surface orientation;

a fin structure extending above the substrate;

a first semiconductor wire formed over the fin structure;

a second semiconductor wire formed over the first semiconductor wire, wherein the first semiconductor wire and the second semiconductor wire are made of different materials;

a gate structure formed over middle portions of the first semiconductor wire and the second semiconductor wire; and

a source/drain (S/D) structure formed at two opposite sides of the first semiconductor wire and the second semiconductor wire, wherein the S/D structure comprises a first portion over sidewalls of the first semiconductor wire and a second portion over sidewalls of the second semiconductor wire, and the first portion is thicker than, or thinner than, the second portion.

13. The semiconductor device structure as claimed in claim 12, wherein the S/D structure comprises silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), germanium arsenide (GaAs), germanium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), or a combination thereof.

14. The semiconductor device structure as claimed in claim 12, further comprising:

a buffer layer formed between the fin structure and the substrate, wherein a lattice constant of the buffer layer is between a lattice constant of the fin structure and a lattice constant of the substrate.

15. The semiconductor device structure as claimed in claim 12, further comprising:

a spacer formed between the gate structure and the S/D structure.

16. A semiconductor device structure, comprising:

a substrate with (110) surface orientation or (111) surface orientation;

a fin structure extending above the substrate, and having a stacked wire structure with a bottom surface;

an isolation structure formed over the substrate; and

a source/drain (S/D) structure formed at two opposite sides of the stacked wire structure, wherein the S/D structure comprises a top flat surface, a sidewall surface, and a rounded corner between the top flat surface and the sidewall surface;

wherein the stacked wire structure comprises a second semiconductor wire over a first semiconductor wire, the S/D structure comprises a first portion over sidewalls of the first semiconductor wire and a second portion over sidewalls of the second semiconductor wire, and the first portion and the second portion of the S/D structure have a periodical wave-like profile.

17. The semiconductor device structure as claimed in claim 16, wherein the S/D structure comprises a sidewall portion over sidewalls of the stacked wire structure and a top portion over a top surface of the stacked wire structure, wherein the sidewall portion has a first thickness along a horizontal direction, the top portion has a second thickness along a vertical direction, and the second thickness is greater than the first thickness.

18. The semiconductor device structure as claimed in claim 16, wherein the first portion and the second portion of the S/D structure are oriented along <

112>

, <

111>

, or <

100>

direction.