Phase-change memory cell having a compact structure

• US 9,735,353 B2
• Filed: 04/13/2016
• Issued: 08/15/2017
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV), Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV), Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Boivin, Philippe, Jeannot, Simon
• Primary Examiner(s): Sefer, A.
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US15/098,025
• Publication Number:
  US 20160380190A1
• Time in Patent Office: 489 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/061 Shaping switching materials
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

Claims

1. A memory cell comprising:

a semiconductor substrate;

a first insulating layer covering a surface of the semiconductor substrate;

an active layer of semiconductor material covering the first insulating layer;

a control gate of a selection transistor, the control gate being formed on the active layer and having a lateral flank;

a trench formed through the active layer, the trench being defined on one side by a lateral flank of the active layer and defined on a bottom side by a top side of the first insulating layer;

a second insulating layer covering the lateral flank of the control gate; and

a variable-resistance element electrically coupled to a first conduction terminal of the selection transistor,

wherein the variable-resistance element is at least partially in the trench and contacting the lateral flank of the active layer in the trench.

2. The memory cell according to claim 1, further comprising:

a trench conductor having a lateral flank, the variable resistance element between the lateral flank of the trench conductor and the lateral flank of the active layer.

3. The memory cell according to claim 1, further comprising:

a conductive layer, contacts an upper portion of the variable-resistance element, and extends longitudinally in a plane parallel to the surface of the substrate.

4. The memory cell according to claim 3, comprising a dielectric trench isolation formed under the conductive layer and having a lateral flank covered by the variable-resistance element.

5. The memory cell according to claim 1, further comprising a silicide barrier positioned between the active layer and the variable-resistance element.

6. The memory cell according to claim 2, further comprising:

a spacer between a wall of the variable resistance element and the trench conductor.

7. A memory comprising:

a plurality of wordlines;

a plurality of bit lines;

a plurality of source lines;

a semiconductor substrate;

a first insulating layer covering a surface of the semiconductor substrate;

a semiconductor active layer covering the first insulating layer; and

at least two memory cells, each of the memory cells including;

a selection transistor that includes a control gate and a first conduction terminal, the control gate being formed on the active layer, having a lateral flank, and being electrically coupled to one of the word lines;

a trench formed through the active layer, the trench being defined on one side by a lateral flank of the active layer and defined on a bottom side by a top side of the first insulating layer;

a second insulating layer covering the lateral flank of the control gate; and

a variable-resistance element electrically coupled to the first conduction terminal of the selection transistor, wherein the variable-resistance element is at least partially in the trench and contacting the lateral flank of the active layer in the trench, the conduction terminal of the selection transistor being electrically coupled to one of the bit lines through the variable-resistance element.

8. The memory according to claim 7, in which:

the at least two memory cells include first and second memory cells, a conductive layer on the variable-resistance elements of the first and second memory elements as a shared trench conductor electrically coupled to one of the same bit lines.

9. The memory according to claim 7, in which a second conduction terminal of the selection transistor of each memory cell is shared with another memory cell of the memory.

10. The memory according to claim 7, in which each of the at least two memory cells includes a trench conductor having a lateral flank covered by the variable-resistance element.

11. The memory according to claim 7, further comprising:

a conductive layer in contact with an upper portion of the variable-resistance element, and extends longitudinally in a plane parallel to the surface of the substrate.

12. The memory according to claim 11, wherein each memory cell includes a dielectric trench isolation formed under the conductive layer of the memory cell and having a lateral flank covered by the variable-resistance element of the memory cell.

13. The memory according to claim 8, further comprising:

a first silicide barrier positioned between the active layer and the variable-resistance element of the first memory cell, the first silicide barrier being impermeable to diffusion of species present in the variable-resistance element of the first memory cell towards the active layer; and

a second silicide barrier positioned between the active layer and the variable-resistance element of the second memory cell, the second silicide barrier being impermeable to diffusion of species present in the variable-resistance element of the second memory cell towards the active layer.

14. The memory according to claim 7, further comprising:

a trench conductor having a lateral flank covered by the variable resistance element.

15. A memory comprising:

a first memory cell that includes;

a selection transistor having a control gate formed on a semiconductor layer and a first conduction terminal formed in the semiconductor layer, the control gate having a lateral flank;

a first insulating layer covering the lateral flank of the control gate; and

a variable-resistance element electrically coupled to and in contact with the first conduction terminal of the selection transistor at a lateral flank of the semiconductor layer, the variable-resistance element extending through the semiconductor layer and covering a lateral flank of the first insulating layer, the first insulating layer extending between the control gate and the variable-resistance element and electrically insulating the control gate from the variable-resistance element.

16. The memory according to claim 15, further comprising:

a second memory cell including;

a selection transistor that includes a control gate and a first conduction terminal, the control gate of the selection transistor of the second memory cell being formed on the semiconductor layer and having a lateral flank;

a second insulating layer covering the lateral flank of the control gate of the selection transistor of the second memory cell; and

a second variable-resistance element electrically coupled to and in contact with the first conduction terminal of the selection transistor of the second memory cell at a lateral flank of the semiconductor layer, the second variable-resistance element extending through the semiconductor layer and covering a lateral flank of the second insulating layer, the second insulating layer extending between the control gate of the selection transistor of the second memory cell and the second variable-resistance element and electrically insulating the control gate of the selection transistor of the second memory cell from the second variable-resistance element.

17. The memory according to claim 16, further comprising:

a shared trench conductor, the first and second variable-resistance elements being formed in a trench in the semiconductor layer, and the shared trench conductor having a first lateral flank covered by the first variable-resistance element and a second lateral flank covered by the second variable-resistance element.

18. The memory according to claim 16, wherein:

the selection transistors of the first and second memory cells share a second conduction terminal;

the selection transistor of the first memory cell includes a channel region positioned under the control gate of the selection transistor of the first memory cell and between the first conduction terminal of the selection transistor of the first memory cell and the second conduction terminal; and

the selection transistor of the second memory cell includes a channel region positioned under the control gate of the selection transistor of the second memory cell and between the first conduction terminal of the selection transistor of the second memory cell and the second conduction terminal.

19. The memory according to claim 15, further comprising:

a semiconductor substrate

a second insulating layer covering a surface of the semiconductor substrate and positioned between the semiconductor layer and the substrate.

20. The memory cell according to claim 15, further comprising a silicide barrier positioned between the semiconductor layer and the variable-resistance element, the silicide barrier being impermeable to diffusion of species present in the variable-resistance element towards the semiconductor layer.

21. The memory cell according to claim 17, further comprising:

a first spacer between a wall of the first variable resistance element and the shared trench conductor; and

a second spacer between a wall of the second variable resistance element and the shared trench conductor.