Cascaded multi-level power converter

• US 9,735,664 B2
• Filed: 01/16/2014
• Issued: 08/15/2017
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Schneider Toshiba Inverter Europe SAS (Toshiba Corporation)
• Original Assignee: Schneider Toshiba Inverter Europe SAS (Toshiba Corporation)
• Inventors: Lavieville, Jean-Paul
• Primary Examiner(s): Laxton, Gary L
• Assistant Examiner(s): Andino, Ivan Laboy
• Application Number:
  US14/654,664
• Publication Number:
  US 20150311776A1
• Time in Patent Office: 1,307 Days
• Field of Search: 363 16- 17, 363 37- 43, 363 52- 55, 363 5601- 5602, 363 65, 363 71, 363 84, 363 89, 363 95- 98, 363123, 363125, 363131-132, 363135-136, 307 82
• CPC Class Codes: H02M 1/007 Plural converter units in cascade push-pull DC/DC converters with pre-regulator H02M3/3374; DC-AC converters following a DC-DC stage including a high frequency transformer H02M7/4807; DC-AC converters following a DC-DC conversion stage generating periodically varying voltages H02M7/4826
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4833 Capacitor voltage balancing
• CPC Class Codes: H02M 7/4837 Flying capacitor converters
• CPC Class Codes: H02M 7/487 Neutral point clamped inverters

Abstract

A multi-level power converter comprising: n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral Point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter); an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted) and ANPC (Active Neutral Point Clamped).

Claims

1. A multilevel power converter comprising:

n input stages, n being greater than or equal to 2, each input stage of rank k, k being 1 through n, having k+1 identical input converters that are connected to one another, each converter being supplied with an input voltage and controlled to apply an electrical potential to an output on the basis of said input voltage;

each input converter of the input stage of rank k−

1 being supplied with a voltage resulting from the electrical potentials applied to two outputs by two converters of input stage of rank k;

an output stage connected to the input stage of rank 1 and having an output converter supplied with a differential voltage resulting from a first electrical potential applied to an output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to an output of a second input converter of the input stage of rank 1, said output converter being controlled to apply an electrical potential to an output;

wherein the input converters exhibit an identical topology, chosen from among architectures of Neutral Point Clamped (NPC), Active Neutral Point Clamped (ANPC) and Neutral Point Piloted (NPP);

wherein the output converter exhibits a different topology than the topology chosen for the input converters, said topology of the output converter being chosen from among architectures of Flying Capacitor (FC), Stacked Multicell Converter (SMC), Neutral Point Clamped (NPC), Neutral Point Piloted (NPP) and Active Neutral Point Clamped (ANPC) type;

wherein the input stage of rank 1 includes only two input converters conformed by the first input converter of the input stage of rank 1 and the second input converter of the input stage of rank 1;

wherein the input stage of rank 2 includes only three input converters conformed by a first input converter of the input stage of rank 2, a second input converter of the input stage of rank 2 and a third input converter of the input stage of rank 2;

wherein the first input converter of the input stage of rank 1 is directly connected to the first and the second input converters of the input stage of rank 2, and the output converter, without any intervening converter; and

wherein the second input converter of the input stage of rank 1 is directly connected to the second and the third input converters of the input stage of rank 2, and the output converter, without any intervening converter.

2. The multilevel power converter as claimed in claim 1, wherein the input converters exhibit a topology of NPP type and in that the output converter exhibits a flying capacitor topology.

3. The multilevel power converter as claimed in claim 1, wherein the input converters exhibit a topology of NPC type and in that the output converter exhibits a flying capacitor topology.

4. The multilevel power converter as claimed in claim 1, wherein the input converters exhibit a topology of ANPC type and in that the output converter exhibits a flying capacitor topology.

5. The multilevel power converter as claimed in claim 1, wherein the input converters exhibit a topology of NPP type and in that the output converter exhibits a topology of SMC type.

6. The multilevel power converter as claimed in claim 1, wherein the input converters exhibit a topology of NPC type and in that the output converter exhibits a topology of SMC type.

7. The multilevel power converter as claimed in claim 1, wherein that the input converters exhibit a topology of ANPC type and in that the output converter exhibits a topology of SMC type.