Low-power clock repeaters and injection locking protection for high-frequency clock distributions

• US 9,735,793 B2
• Filed: 12/08/2015
• Issued: 08/15/2017
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Cheng Chang, Kevin Yi, Islam, Muhammad Z.
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US14/962,696
• Publication Number:
  US 20170163274A1
• Time in Patent Office: 616 Days
• Field of Search: 327147
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H03K 5/15013 with more than two outputs
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).

Claims

1. A method for preventing injection locking, comprising:

generating an offset clock signal having a programmable frequency f_OS;

mixing the offset clock signal with an output signal from a clock repeater circuit having a central frequency f_O to generate an active forcing signal having an output frequency f_O±

f_OS; and

connecting the active forcing signal to a guard ring disposed around the clock repeater circuit to deviate an injecting signal having an undesired injecting source frequency f_x from the clock repeater outside of an injection locking range for the clock repeater circuit.

2. The method of claim 1, where generating the offset clock signal comprises generating a low frequency offset clock signal by dividing a phase lock loop (PLL) reference frequency source signal.

3. The method of claim 1, where mixing the offset clock signal comprises supplying a passive mixer circuit with the output signal and the offset clock signal to generate the active forcing signal.

4. The method of claim 1, where connecting the active forcing signal to the guard ring locks the injecting signal into a new signal having a frequency beyond the injection locking range.

5. The method of claim 1, where the guard ring is formed to surround and shield a differential-mode RLC network circuit in the clock repeater circuit from injection locking inductive coupling effects.

6. The method of claim 1, where the clock repeater circuit comprises a passive differential-mode RLC network coupled to receive first and second input clock signals to provide clock signal gain boosting at a predetermined operating frequency range and clock signal attenuation out of the predetermined operating frequency range, thereby generating first and second output clock signals.

7. An integrated circuit device, comprising:

a differential-mode RLC network circuit coupled to receive a first and second input clock signals for generating first and second output clock signals;

a low frequency clock for generating an offset clock signal;

a passive mixer circuit coupled to mix the offset clock signal with the first and second output clock signals from the differential-mode RLC network circuit to generate an active forcing signal; and

an active guard ring structure formed to surround and shield the differential-mode RLC network circuit from injection locking inductive coupling effects, where the active guard ring structure driven by the active forcing signal to deviate an injecting signal having an undesired injecting source frequency from the differential-mode RLC network circuit outside of an injection locking range for the differential-mode RLC network circuit.

8. The integrated circuit device of claim 7, further comprising a passive guard ring structure formed to surround and shield the differential-mode RLC network circuit, where the passive guard ring structure is connected to a ground reference voltage supply.

9. The integrated circuit device of claim 7, where the differential-mode RLC network circuit comprises:

a programmable shunt capacitor coupled between a positive clock output line and a negative clock output line;

a first resonant gain boost circuit connected between a positive clock input line and a first control voltage, the first resonant gain boost circuit comprising a first inductor-capacitor tank and first resistive voltage divider circuit for providing bias control and clock signal gain boosting to a first output clock signal at the positive clock output line at a predetermined operating frequency range; and

a second resonant gain boost circuit connected between a negative clock input line and a second control voltage, the second resonant gain boost circuit comprising a second inductor-capacitor tank and second resistive voltage divider circuit for providing bias control and clock signal gain boosting to a second output clock signal at the negative clock output line at the predetermined operating frequency range.

10. The integrated circuit device of claim 9, where the first control voltage and second control voltage comprise a shared reference voltage.

11. The integrated circuit device of claim 9, where the first control voltage and second control voltage comprise separate control voltages which are applied to correct duty cycle distortions on the first and second input clock signals.

12. The integrated circuit device of claim 7, where the passive mixer circuit is coupled to receive the first output clock signal as a positive clock signal having a first frequency f_O from a positive clock output line of the differential-mode RLC network circuit and to receive the offset clock signal having an offset frequency f_OS from the low frequency clock.

13. The integrated circuit device of claim 7, where the passive mixer circuit is coupled to receive the second output clock signal as a negative clock signal having a first frequency f_O from a negative clock output line of the differential-mode RLC network circuit and to receive the offset clock signal having an offset frequency f_OS from the low frequency clock.