Coherent transceiver architecture

• US 9,735,881 B1
• Filed: 05/06/2016
• Issued: 08/15/2017
• Est. Priority Date: 11/29/2012
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Quiroga, Pablo Gustavo, Crivelli, Diego Ernesto, Lopez, Ramiro Rogelio, Finochietto, Jorge Manuel, Swenson, Norman L., Voois, Paul, Hueda, Mario Rafael, Morales, Adrin Ulises, del Barco, Martin Ignacio, Asinari, Martin Carlos, Paredes, Federico Nicolas, Taddei, Alfredo Javier, Bruni, Mauro M., Morero, Damian Alfonso, Ramos, Facundo Abel Alcides, Carrer, Hugo Santiago, Gutnik, Vadim, Ferster, Mara Laura, Serrano, Elvio Adrian, Arenas, Roman Antonio, Schwoykoski, Alejandro Javier, Schnidrig, Matias German, Agazzi, Oscar Ernesto
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/148,645
• Time in Patent Office: 466 Days
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04B 10/516 Details of coding or modulation
• CPC Class Codes: H04B 10/61 Coherent receivers
• CPC Class Codes: H04L 7/0075 with photonic or optical means

Abstract

A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Claims

1. An optical communication system comprising:

a fabric interface to receive an input data signal from a host device;

a physical layer processor to map and frame the input data signal into a digital transmit signal;

a coherent transmitter, comprising;

an egress signal path comprising a plurality of egress path clock domains including;

an egress host interface clock domain including an egress host-side interface operating at a first sampling rate according to a first clock signal the egress host-side interface configured to receive the digital transmit signal,

an egress digital signal processor clock domain including an egress digital signal processor operating at a second sampling rate according to a second clock signal, the egress digital signal processor to modulate the digital data signal, and

a digital-to-analog converter clock domain including a digital-to-analog converter operating at a third sampling rate according to a third clock signal, the digital-to-analog converter to output an analog signal vector to an egress line-side interface, wherein the first sample rate, the second sampling rate, and the third sampling rate are different; and

clock and timing circuitry configured to receive a single reference clock signal and to derive the first clock signal, the second clock signal, and the third clock signal from the single reference clock signal; and

an optical module to convert the analog signal vector to an optical signal suitable for transmission over an optical network operating at 100 Gigahertz or higher.

2. The optical communication system of claim 1, wherein the egress digital signal processor clock domain further comprises:

an egress interpolator filter to perform a sampling rate conversion between samples processed in the digital signal processor clock domain and samples provided to the digital-to-analog converter clock domain.

3. The optical communication system of claim 1, wherein the second clock signal of the digital signal processing clock domain and the third clock signal of the digital-to-analog converter clock domain are rationally related.

4. The optical communication system of claim 1, wherein the egress signal path further comprises:

an egress-side data storage buffer configured to prevent loss of data samples when an egress path signal transitions between respective sampling rates.

5. The optical communication system of claim 4, wherein the egress-side data storage buffer between the two adjacent egress path clock domains provides a feedback signal based on a buffer fill level, the feedback signal to adjust a frequency of a modified egress path clock signal provided to at least one of the two adjacent egress path clock domains.

6. The optical communication system of claim 1, wherein the clock and timing circuitry comprises:

an egress line-side phase locked loop to receive the single reference clock signal and to generate an egress line-side reference clock; and

one or more clock frequency divider elements coupled to the egress line-side phase locked loop to generate one of the first, second, and third clock signals based on the egress line-side reference clock.

7. The optical communication system of claim 1, wherein the clock and timing circuitry comprises:

an egress host-side phase locked loop to receive the single reference clock signal and to generate an egress host-side reference clock; and

one or more clock frequency divider elements coupled to the egress host-side phase locked loop to generate one of the first, second, and third clock signals based on the egress host-side reference clock.

8. An optical communication system, comprising:

an optical module to convert an optical signal received over an optical network operating at 100 Gigahertz or higher to an analog signal vector;

a coherent receiver comprising;

an ingress signal path comprising a plurality of ingress path clock domains including;

an ingress analog-to-digital converter clock domain including an analog-to-digital converter operating at a first sampling rate according to a first clock signal, the analog-to-digital converter to convert the analog signal vector to a digital signal vector;

an ingress digital signal processor clock domain including an ingress digital signal processor operating at a second sampling rate according to a second clock signal, the ingress digital signal processor to demodulate the digital signal vector to generate a demodulated digital signal vector; and

an ingress host interface clock domain including an ingress host interface operating at a third sampling rate according to a third clock signal, the ingress host interface to output the demodulated digital signal, wherein the first, second, and third sampling rates are different;

clock and timing circuitry configured to receive a single reference clock signal and to derive the first clock signal, the second clock signal, and the third clock signal from the single reference clock; and

a physical layer processor to de-map and de-frame the demodulated digital signal vector into a output data signal; and

a fabric interface to transmit the output data signal to a host device.

9. The optical communication system of claim 8, wherein the ingress digital signal processor clock domain further comprises:

an ingress interpolator filter to perform a sampling rate conversion between samples received from the analog-to-digital converter clock domain and samples processed in the ingress digital signal processor clock domain.

10. The optical communication system of claim 9, wherein the second clock of the digital signal processing clock domain and the first clock of the analog-to-digital converter clock domain are rationally related.

11. The optical communication system of claim 8, the ingress interpolator receives an input block size having a variable number of input samples and outputs an output block having a fixed number of samples based on a parallelization factor.

12. The optical communication system of claim 11, wherein the ingress signal path further comprises:

an ingress-side data storage buffer configured to prevent loss of data samples when an ingress path signal transitions between respective sampling rates.

13. The optical communication system of claim 12, wherein the ingress-side data storage buffer provides a feedback signal representing a buffer fill level, the feedback signal to adjust a frequency of one of the first, second, and third clock signals.

14. The optical communication system of claim 8, wherein the clock and timing circuitry comprises:

an ingress line-side phase locked loop to receive the single reference clock signal and to generate an ingress line-side reference clock; and

one or more clock frequency divider elements coupled to the ingress line-side phase locked loop to generate one of the first, second, and third clock signals based on the ingress line-side reference clock.

15. The optical communication system of claim 8, wherein the clock and timing circuitry comprises:

an ingress host-side phase locked loop to receive the single reference clock signal and to generate an ingress host-side reference; and

one or more clock frequency divider elements coupled to the ingress host-side phase locked loop to generate one of the first, second, and third clock signals based on the ingress host-side reference clock.

16. The optical communication system of claim 8, wherein the ingress digital signal processor clock domain further comprises:

a bulk chromatic dispersion equalizer to compensate for an estimated amount of chromatic dispersion, wherein the bulk chromatic dispersion equalizer operates according to a fourth clock signal derived from one of the first, second, and third clock signals, and wherein a frequency of the fourth clock signal is determined based on the estimated amount of chromatic dispersion.

17. The optical communication system of claim 8, wherein the ingress signal path further comprises a plurality of carrier recovery stages including:

a coarse carrier recovery stage configured to determine and compensate for frequency offsets in a carrier signal greater than a specified threshold;

a feedback fine carrier recovery stage following the coarse carrier recovery stage, the feedback fine carrier recovery stage comprising a phase domain decision directed phase locked loop to further correct for the frequency offsets in the carrier signal; and

a feedforward fine carrier recovery stage following the feedback fine carrier recovery stage to perform a blind phase search carrier recovery to further correct for the offsets in the carrier signal.

18. The optical communication system of claim 8, wherein the ingress signal path further comprises:

a fiber length estimator to estimate an amount of chromatic dispersion introduced by an the optical network;

a cascaded bulk chromatic dispersion equalizer comprising a first stage and a second stage, the bulk chromatic dispersion equalizer configured to compensate for the estimated amount of chromatic dispersion, wherein the bulk chromatic dispersion equalizer operates in one of a plurality of modes based on the estimated amount of chromatic dispersion, and wherein the first stage of the bulk chromatic dispersion equalizer is bypassed and powered down and the second stage of the bulk chromatic dispersion equalizer is applied when operating in a first mode of the plurality of modes, and wherein both the first stage and the second stage are applied when operating in a second mode of the plurality of modes.

19. An optical communication system, comprising:

an ingress optical module to convert an ingress optical signal received over an optical network operating at 100 Gigahertz or higher to an ingress analog signal vector;

a coherent receiver comprising;

an ingress signal path comprising a plurality of ingress path clock domains including;

an analog-to-digital converter clock domain including an analog-to-digital converter operating at a first sampling rate according to a first clock signal, the analog-to-digital converter to convert the ingress analog signal vector to an ingress digital signal vector;

an ingress digital signal processor clock domain including an ingress digital signal processor operating at a second sampling rate according to a second clock signal, the ingress digital signal processor to demodulate the ingress digital signal vector to generate a demodulated digital signal vector; and

an ingress host interface clock domain including an ingress host interface operating at a third sampling rate according to a third clock signal, the ingress host interface to output the demodulated digital signal, wherein the first, second, and third sampling rates are different;

ingress clock and timing circuitry configured to receive a single reference clock signal and to derive the first clock signal, the second clock signal, and the third clock signal from the single reference clock; and

an ingress physical layer processor to de-map and de-frame the demodulated digital signal vector into a output data signal;

an ingress fabric interface to transmit the output data signal to a host device;

an egress fabric interface to receive an input data signal from the host device;

an egress physical layer processor to map and frame the input data signal into an egress digital signal;

a coherent transmitter, comprising;

an egress signal path comprising a plurality of egress path clock domains including;

an egress host interface clock domain including an egress host-side interface operating at a fourth sampling rate according to a fourth clock signal the egress host-side interface configured to receive the egress digital signal,

an egress digital signal processor clock domain including an egress digital signal processor operating at a fifth sampling rate according to a fifth clock signal, the egress digital signal processor to modulate the egress digital signal, and

a digital-to-analog converter clock domain including a digital-to-analog converter operating at a sixth sampling rate according to a sixth clock signal, the digital-to-analog converter to output an egress analog signal vector to an egress line-side interface, wherein the fourth sample rate, the fifth sampling rate, and the sixth sampling rate are different; and

egress clock and timing circuitry configured to receive the single reference clock signal and to derive the fourth clock signal, the fifth clock signal, and the sixth clock signal from the single reference clock signal; and

an egress optical module to convert the egress analog signal vector to an egress optical signal suitable for transmission over the optical network.

20. The optical communication system of claim 19, wherein the second clock of the ingress digital signal processing clock domain and the first clock of the analog-to-digital converter clock domain are rationally related, and wherein the fifth clock of the egress digital signal processing clock domain and the fourth clock of the analog-to-digital converter clock domain are rationally related.