Communication channel calibration using feedback

• US 9,735,898 B2
• Filed: 09/22/2015
• Issued: 08/15/2017
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kim, Jun, Richardson, Wayne S., Chiu, Glenn
• Primary Examiner(s): Raymond, Edward
• Application Number:
  US14/861,573
• Publication Number:
  US 20160087733A1
• Time in Patent Office: 693 Days
• Field of Search: 702 69, 702 66, 702 64, 702182-185
• CPC Class Codes: H04B 17/11 for calibration
• CPC Class Codes: H04L 2025/03802 Signalling on the reverse channel
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 5/1438 Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

Claims

1. An integrated circuit (IC) chip, comprising:

an interface circuit including a transmitter configured to transmit data signals along a wired link to a destination IC chip, the data signals carrying a sequence of data symbols;

calibration circuitry including a receiver, to receive timing drift information from the destination IC chip, the timing drift information associated with sensed phase information of the data signals received at the destination IC chip; and

logic to adjust a timing parameter associated with the transmitted data signals based on the received timing drift information.

2. The IC chip of claim 1, embodied as an IC memory controller.

3. The IC chip of claim 1, wherein the interface circuit includes multiple input/output (I/O) circuits, each I/O circuit including a respective transmitter for interfacing with respective wired links, and wherein the timing parameter is adjusted for each of the multiple I/O circuits.

4. The IC chip of claim 3, wherein the transmitters in the multiple I/O circuits transmit data signals with a data rate of greater than one gigabit per second.

5. The IC chip of claim 1, wherein the receiver is operable to decompose a communication packet received from the destination IC chip, the packet including the timing information.

6. The IC chip of claim 1, including a port coupled to the receiver for communication with the destination IC chip, the receiver operable to receive the information using the port.

7. The IC chip of claim 6, wherein the port comprises a serial port.

8. The IC chip of claim 6, further comprising a pin coupled to the port, and wherein the pin is used for multiple functions.

9. An integrated circuit (IC) chip, comprising:

an interface circuit including a transmitter configured to transmit data signals along a wired link, the data signals carrying a sequence of data symbols;

calibration circuitry including

a receiver including a port, to receive timing drift information from a destination of the data signals, wherein the port is coupled to a pin on the IC chip, and wherein the pin comprises a scan out port; and

logic to adjust a timing parameter associated with the transmitted data signals based on the received timing drift information.

10. The IC chip of claim 9, wherein the transmitter transmits data signals with a data rate of greater than one gigabit per second, and the port comprises a serial port having a data rate slower than the data rate of the data signals.

11. The IC chip of claim 9, embodied as a DRAM memory controller.

12. A method of operation in an integrated circuit (IC) memory controller, the method comprising:

transmitting data signals along a wired link, the data signals including a sequence of data symbols representing data;

calibrating a timing parameter associated with the data signals by

receiving sensed information from a destination of the data signals, the sensed information associated with a parameter of the data signals received at the destination; and

adjusting a timing parameter associated with the transmitted data signals based on the received sensed information.

13. The method of claim 12, wherein the sensed information comprises phase information associated with the data signals relative to a reference clock.

14. The method of claim 12, wherein the sensed information comprises equalization characteristics of the data signals.

15. The method of claim 12, wherein the sensed information comprises amplitude information associated with the data signals.

16. The method of claim 12, wherein the receiving comprises decomposing a communication packet including the sensed information.

17. The method of claim 12, including receiving the sensed information using a serial port.

18. The method of claim 17, wherein the transmitting comprises transmitting the data signals with a data rate of greater than one gigabit per second and the serial port operates at a data rate slower than the data rate of the data signals.

19. The method of claim 12, including receiving the sensed information using a port coupled to a pin on the IC memory controller, and wherein the pin is used for multiple functions.

20. The method of claim 12, including receiving the sensed information using a port coupled to a pin on the IC memory controller, and wherein the pin is used by a scan out port on the IC memory controller.