Continuous time linear equalizer that uses cross-coupled cascodes and inductive peaking
First Claim
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1. An equalizer, comprising:
- a differential input comprising a first input and a second input;
a differential output comprising a first output and a second output;
a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD;
a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD;
a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor;
a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor;
a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input;
a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input;
a first current source coupled between a source of the first lower transistor and ground; and
a second current source coupled between a source of the second lower transistor and ground.
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Abstract
The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.
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Citations
14 Claims
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1. An equalizer, comprising:
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a differential input comprising a first input and a second input; a differential output comprising a first output and a second output; a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD; a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD; a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor; a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor; a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input; a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input; a first current source coupled between a source of the first lower transistor and ground; and a second current source coupled between a source of the second lower transistor and ground. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system, comprising:
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at least one processor; at least one memory coupled to the at least one processor; and an equalizer that facilitates communications among components in the system, wherein the equalizer includes; a differential input comprising a first input and a second input; a differential output comprising a first output and a second output; a first inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD; a second inductor with a lower terminal and an upper terminal, wherein the upper terminal is coupled to VDD; a first resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the first inductor; a second resistor with an upper terminal and a lower terminal, wherein the upper terminal is coupled to the lower terminal of the second inductor; a first cascode comprising a first upper transistor and a first lower transistor, wherein a drain of the first upper transistor is coupled to the lower terminal of the first resistor and the first output, wherein a gate of the first upper transistor is cross-coupled to the lower terminal of the second inductor, wherein a source of the first upper transistor is coupled to a drain of the first lower transistor, and wherein a gate of the first lower transistor is coupled to the first input; a second cascode comprising a second upper transistor and a second lower transistor, wherein a drain of the second upper transistor is coupled to the lower terminal of the second resistor and the second output, wherein a gate of the second upper transistor is cross-coupled to the lower terminal of the first inductor, wherein a source of the second upper transistor is coupled to a drain of the second lower transistor, and wherein a gate of the second lower transistor is coupled to the second input; a first current source coupled between a source of the first lower transistor and ground; and a second current source coupled between a source of the second lower transistor and ground. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification