General input/output architecture, protocol and related methods to implement flow control

• US 9,736,071 B2
• Filed: 12/22/2014
• Issued: 08/15/2017
• Est. Priority Date: 08/24/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Lee, David, Fanning, Blaise, Harriman, David
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/580,073
• Publication Number:
  US 20150178241A1
• Time in Patent Office: 967 Days
• Field of Search: None
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4252 using a handshaking protocol
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes

Abstract

An enhanced general input/output communication architecture, protocol and related methods are presented.

Claims

1. An apparatus comprising:

a device comprising logic to;

receive a flow control packet over a general purpose I/O interconnect, wherein the interconnect is to comprise a differential, point-to-point serial data link;

maintain one or more flow control credit values, based on information in the flow control packet, to represent buffer capacity of a receiver for each of a plurality of virtual channels, wherein flow control credit values of the plurality of virtual channels are maintained for each of a plurality of flow control credit types and the plurality of flow control credit types comprise posted request headers, posted request data payload, non-posted request headers, non-posted request data payload, completion headers, and completion data payload; and

determine whether to send a transaction layer packet to the receiver using the virtual channel based at least in part on the flow control credit value.

2. The apparatus of claim 1, wherein the interconnect comprises at least one of a physical layer to support a Peripheral Component Interconnect Express (PCIe)-based protocol layer and a physical layer including one or more other protocols.

3. The apparatus of claim 1, wherein the interconnect is compliant with a PCIe-based protocol.

4. The apparatus of claim 1, wherein the flow control credit limit values represent a total number of flow control credits made available for at least one of the plurality of virtual channels.

5. The apparatus of claim 4, wherein the flow control information indicates the flow control credit limit value.

6. The apparatus of claim 1, wherein the logic is to maintain a value of flow control credits consumed since initialization of at least one of the plurality of virtual channels.

7. The apparatus of claim 6, wherein determining whether to send a data packet is to be based at least in part on the value of the flow control credits consumed.

8. The apparatus of claim 7, wherein the data packet is to be sent when a sum of an amount of flow control credits associated with the data packet and the flow control credits consumed does not exceed a flow control credit limit for a corresponding one of the plurality of virtual channels.

9. The apparatus of claim 7, wherein the data packet is to be delayed when a sum of an amount of flow control credits associated with the data packet and the flow control credits consumed exceeds a flow control credit limit a corresponding one of the plurality of virtual channels.

10. The apparatus of claim 1, wherein the plurality of virtual channels includes at least eight virtual channels.

11. The apparatus of claim 1, wherein the plurality of virtual channels includes a default virtual channel.

12. The apparatus of claim 1, wherein the logic is to maintain a respective flow control register for each of the plurality of virtual channels.

13. An apparatus comprising logic, implemented at least in part in hardware, to be coupled to an interconnect to:

maintain a count of flow control credits to be granted to a transmitter for each of a plurality of virtual channels, wherein a count is maintained for each of a plurality of flow control credit types and the plurality of flow control credit types comprise posted request headers, posted request data payload, non-posted request headers, non-posted request data payload, completion headers, and completion data payload;

assemble a flow control packet to include flow control information to represent buffer capacity associated with at least one of the plurality of virtual channels; and

send the flow control packet to the transmitter.

14. The apparatus of claim 13, wherein the interconnect comprises at least one of a physical layer to support a PCIe-based protocol layer and a physical layer including one or more other protocols.

15. The apparatus of claim 13, wherein the interconnect is compliant with a PCIe-based protocol.

16. The apparatus of claim 13, wherein the logic is to participate in initialization of flow control for at least a particular one of the plurality of virtual channels, and the flow control packet is to be sent in association with the initialization and is to identify a flow control credit limit for the particular virtual channel.

17. The apparatus of claim 13, wherein the flow control packet is to update a value of a flow control credit limit for at least a particular one of the plurality of virtual channels.

18. The apparatus of claim 13, wherein the flow control packet is to include an identifier of a corresponding one of the plurality of virtual channels.

19. The apparatus of claim 13, wherein the flow control packet comprises a data link layer packet.

20. A system comprising:

an interconnect;

a first device; and

a second device communicatively coupled to the first device using the interconnect, the second device to;

receive a flow control packet over a general purpose I/O interconnect, wherein the interconnect is to comprise a differential, point-to-point serial data link;

maintain one or more flow control credit values, based on information in the flow control packet, to represent buffer capacity of a receiver for each of a plurality of virtual channels, wherein flow control credit values of the plurality of virtual channels are to be maintained for each of a plurality of flow control credit types and the plurality of flow control credit types comprise posted request headers, posted request data payload, non-posted request headers, non-posted request data payload, completion headers, and completion data payload; and

determine whether to send a transaction layer packet to the receiver using the virtual channel based at least in part on the flow control credit value.

21. The system of claim 20, wherein the interconnect comprises a Peripheral Component Interconnect Express (PCIe).

22. The system of claim 20, wherein the device comprises an endpoint.

23. The system of claim 20, wherein the second device comprises a switch.

24. The system of claim 20, wherein the second device comprises a root complex.