Method and structure of MEMS PLCSP fabrication

• US 9,738,510 B1
• Filed: 06/25/2015
• Issued: 08/22/2017
• Est. Priority Date: 10/04/2013
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Lee, Chien Chen
• Primary Examiner(s): Tran, Minh-Loan
• Application Number:
  US14/750,820
• Time in Patent Office: 789 Days
• Field of Search: None
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0242 Gyroscopes
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 3/0035 Constitution or structural means for controlling the movement of the flexible or deformable elements
• CPC Class Codes: B81B 3/0062 Devices moving in two or more dimensions, i.e. having special features which allow movement in more than one dimension
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81C 1/00134 comprising flexible or deformable structures manufacture of MEMS devices for specific applications, see relevant places, e.g. gyroscopes G01C19/5719, pressure sensors G01L9/0042, accelerometers G01P15/0802, acoustic transducers or diaphragms therefor H04R31/00
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis
• CPC Class Codes: G01C 19/5783 Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
• CPC Class Codes: G01L 19/147 Details about the mounting of the sensor to support or covering means
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H04R 2201/003 Mems transducers or their use of the electrostatic type H04R19/005
• CPC Class Codes: H04R 31/00 Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor manufacture of microstructural arrangements of deformable or non-deformable structures in general B81C1/00182

Abstract

A method and structure for a PLCSP (Package Level Chip Scale Package) MEMS package. The method includes providing a MEMS chip having a CMOS substrate and a MEMS cap housing at least a MEMS device disposed upon the CMOS substrate. The MEMS chip is flipped and oriented on a packaging substrate such that the MEMS cap is disposed above a thinner region of the packaging substrate and the CMOS substrate is bonding to the packaging substrate at a thicker region, wherein bonding regions on each of the substrates are coupled. The device is sawed to form a package-level chip scale MEMS package.

Claims

1. A package-level chip scale MEMS packaged device comprising:

a MEMS chip comprising a CMOS substrate having a top surface having a first portion and a second portion and comprising a cap disposed upon the first portion of the CMOS substrate, wherein the CMOS substrate is associated with a first thickness, wherein the cap is associated with a second thickness, wherein the cap and the first portion of the top surface form an enclosed cavity, wherein at least a MEMS device is formed on the first portion of the top surface and disposed within the enclosed cavity, wherein the second portion of the top surface of the CMOS substrate is substantially free of the cap and includes at least a first bonding region;

a packaging substrate having a top surface, the top surface having a first portion and a second portion, wherein the first portion is characterized by a third thickness, wherein the second portion is characterized by a fourth thickness, wherein the third thickness exceeds the fourth thickness by at least the second thickness associated with the cap, wherein the first portion of the top surface of the packaging substrate includes at least a second bonding region;

wherein the MEMS chip is oriented relative to the packaging substrate such that the second portion of the top surface of the CMOS substrate is opposed to the first portion of the top surface of the packaging substrate, and such that the cap is disposed above the second portion of the top surface of the packaging substrate; and

wherein the first bonding region is bonded to the second bonding region.

2. The device of claim 1 wherein a sum of the first thickness for the CMOS substrate and the second thickness for the cap is within a range of about 450 microns to about 500 microns.

3. The device of claim 1 wherein the first thickness for the CMOS substrate is within a range of about 300 microns to about 400 microns.

4. The device of claim 1 wherein the second thickness for the cap is within a range of about 100 microns to about 150 microns.

5. The device of claim 1 wherein the third thickness associated with the first portion of the packaging substrate is within a range of about 100 microns to about 200 microns.

6. The device of claim 1 wherein a thickness of the package-level chip scale MEMS package is within a range of about 650 microns to about 750 microns.

7. The device of claim 1

wherein the top surface of the CMOS substrate also includes a third portion, and wherein third portion of the top surface of the CMOS substrate is substantially free of the cap and includes at least a third bonding region;

wherein the top surface of the packing substrate also includes a third portion, wherein the third portion is characterized by the third thickness, and wherein the third portion of the top surface of the packaging substrate includes at least a fourth bonding region;

wherein the MEMS chip is oriented relative to the packing substrate such that the third portion of the top surface of the CMOS substrate is opposed to the third portion of the top surface of the packaging substrate; and

wherein the third bonding region is bonded to the fourth bonding region.

8. The device of claim 7

wherein the first portion of the top surface of the CMOS substrate is laterally disposed between the second portion of the top surface of the CMOS substrate and the third portion of the top surface of the CMOS substrate.

9. The device of claim 8

wherein the first bonding region is electrically coupled to the second bonding region;

and

wherein the third bonding region is electrically coupled to the fourth bonding region.

10. The device of claim 9

wherein the first bonding region is electrically coupled to the second bonding region substantially free of wires;

and

wherein the third bonding region is electrically coupled to the fourth bonding region substantially free of wires.

11. The device of claim 1

wherein the second portion of the CMOS substrate is characterized by a first area;

wherein the MEMS chip is characterized by a second area; and

wherein the first area is larger than the second area within a range of about 40% to about 50%.

12. The device of claim 1 wherein the MEMS device is selected from a group consisting of:

an accelerometer, a gyroscope, a magnetometer, a pressure sensor.

13. The device of claim 1 wherein the second bonding region comprises a pre-solder bump.

14. The device of claim 1 wherein the packaging substrate comprises a bottom surface having a plurality of contacts disposed thereon.

15. The device of claim 14 further comprising an encapsulation material disposed over the MEMS chip and the packaging substrate, wherein the plurality of contacts are substantially free of the encapsulation material.

16. The device of claim 1 wherein the first bonding region is electrically coupled to the second bonding region.

17. The device of claim 16 wherein the first bonding region is electrically coupled to the second bonding region substantially free of wires.

18. The device of claim 16 wherein the first bonding region is electrically coupled to the second bonding region via solder.

19. The device of claim 1 wherein the cap is physically bonded to the second portion of the top surface of the packaging substrate.

20. The device of claim 1 wherein the cap is approximately laterally centered upon the CMOS substrate.