Test messaging demodulate and modulate on separate power pads

• US 9,739,832 B2
• Filed: 07/08/2016
• Issued: 08/22/2017
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US15/205,527
• Publication Number:
  US 20160320453A1
• Time in Patent Office: 410 Days
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

The present disclosure describes a novel method and apparatus for using a device'"'"'s power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

Claims

1. An integrated circuit comprising:

A. a first power pad, a second power pad, and a ground pad;

B. functional circuitry having functional input and output leads and having a first power lead, a second power lead, and a ground lead coupled to the power and ground pads;

C. test circuitry having test leads connected to the functional circuitry and having a first device test lead and a second device test lead extending from the test circuitry, the first and second device test leads being free of the functional input and output leads;

D. input test messaging and control circuitry having a test input lead and a test circuitry lead connected to the first device test lead;

E. output test messaging and control circuitry having a test output lead and a test circuitry lead connected to the second device test lead;

F. demodulation circuitry having an input coupled to the first power pad and an output coupled to the test input lead of the input test messaging and control circuitry;

G. modulation circuitry having an output coupled to the second power pad and an input coupled to the test output lead of the output test messaging and control circuitry;

H. first filter circuitry connecting the first power pad to the first power input lead between the input of the demodulation circuitry and the first power lead; and

I. second filter circuitry connecting the second power pad to the second power input lead between the output of the modulation circuitry and the second power lead.

2. The integrated circuit of claim 1 including a capacitor connecting the input of the demodulation circuitry to the first power terminal.

3. The integrated circuit of claim 1 including a capacitor connecting the output of the modulation circuitry to the second power terminal.