Vector generate mask instruction

• US 9,740,482 B2
• Filed: 12/05/2014
• Issued: 08/22/2017
• Est. Priority Date: 01/23/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Enenkel, Robert F., Schwarz, Eric M., Slegel, Timothy J.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/561,815
• Publication Number:
  US 20150143075A1
• Time in Patent Office: 991 Days
• Field of Search: None
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/30098 Register arrangements

Abstract

A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Claims

1. A method of executing a machine instruction in a central processing unit, the method comprising:

obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising;

at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation;

a first register field to be used to designate a first register, the first register comprising a first operand, the first operand comprising a vector having a plurality of elements;

a first field to specify a starting position; and

a second field to specify an ending position; and

executing the machine instruction, the executing comprising;

generating a plurality of masks for the plurality of elements of the first operand, the generating for a mask comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position.

2. The method of claim 1, wherein the one or more positions comprises one or more bits, and wherein the starting position specifies a first selected bit in the mask and the ending position specifies a second selected bit in the mask.

3. The method of claim 2, wherein the first field comprises a first unsigned integer value specifying the starting position, and the second field comprises a second unsigned integer value specifying the ending position.

4. The method of claim 1, wherein the generating comprises setting other positions in the mask to zero.

5. The method of claim 1, wherein the executing further comprises:

determining whether the starting position is greater than the ending position; and

based on the starting position being greater than the ending position, a range of positions wraps at a maximum position for a size of an element of the plurality of elements of the first operand.

6. The method of claim 1, wherein the machine instruction further comprises a field to specify the size of an element of the plurality of elements of the first operand.

7. The method of claim 1, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register.

8. The method of claim 1, wherein one or more masks of the plurality of masks generated by the machine instruction are to be used by one or more other instructions.