Method and apparatus for asynchronous processor removal of meta-stability

• US 9,740,487 B2
• Filed: 09/08/2014
• Issued: 08/22/2017
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Huang, Tao, Zhang, Qifan, Shi, Wuxian, Ge, Yiqun, Tong, Wen
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US14/480,522
• Publication Number:
  US 20150074445A1
• Time in Patent Office: 1,079 Days
• Field of Search: 712 18, 712201
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 2009/3883 Two-engine architectures, i.e. stand-alone processor acting as a slave processor
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage'"'"'s necessary delay(s) or may be programmably configured.

Claims

1. A clock-less asynchronous processing system, comprising:

a processing pipeline having a plurality of successive processing stages, each processing stage comprising,

asynchronous logic circuitry configured to process input data and output processed data,

a data storage element coupled to the asynchronous logic circuitry and configured to receive and store the processed output data in response to a current stage active complete signal, and

a self-clocked generator configured to receive a previous stage active complete signal, generate the current stage active complete signal in response thereto, and output the current stage active complete signal to the data storage element and to a next processing stage.

2. The processing system in accordance with claim 1 wherein the self-clocked generator is programmable and configured to delay the received previous stage active complete signal by a first predetermined delay in order to generate the current stage active complete signal.

3. The processing system in accordance with claim 2 wherein the first predetermined delay is programmable.

4. The processing system in accordance with claim 1 wherein the asynchronous logic circuitry includes a processing delay associated therewith, the processing delay representative of an amount of time required by the asynchronous logic circuitry to process the input data and output the processed data.

5. The processing system in accordance with claim 4 wherein the self-clocked generator is configured to delay the received previous stage active complete signal by a first predetermined delay in order to generate the current stage active complete signal, and wherein the first predetermined delay is in addition to the processing delay.

6. The processing system in accordance with claim 1 wherein the self-clocked generator is further configured to select one of a plurality of available clocking signals for output as the current stage active complete signal.

7. The processing system in accordance with claim 6 wherein the self-clocked generator comprises a multiplexer configured to:

receive the plurality of available clocking signals;

receive a configuration parameter signal operable for selecting one of the plurality of available clocking signals; and

output the selected clocking signal.

8. The processing system in accordance with claim 7 wherein each of the plurality of available clocking signals is a delayed version of the previous stage active complete signal with a predetermined delay.

9. A method of operating a clock-less asynchronous processing system comprising a processing pipeline having a plurality of successive processing stages, each processing stage further comprising, asynchronous logic circuitry, a data storage element coupled to an output of the asynchronous logic circuitry and a self-clocked generator, the method comprising:

receiving input data from a previous stage data storage element;

receiving, at the self-clocked generator, a previous stage active complete signal;

processing the received input data through the asynchronous logic circuitry and outputting processed data;

generating a current stage active complete signal in response to the received previous stage active complete signal and transmitting the current stage active complete signal to a next successive processing stage; and

storing the processed data in a current data storage element in response to the current stage active complete signal.

10. The method in accordance with claim 9 further comprising:

outputting the current stage active complete signal after a first predetermined delay after receiving the previous stage active complete signal.

11. The method in accordance with claim 10 wherein the first predetermined delay is programmable.

12. The method in accordance with claim 9 a wherein the asynchronous logic circuitry includes a processing delay associated therewith, the processing delay representative of an amount of time required by the asynchronous logic circuitry to process the input data and output the processed data.

13. The method in accordance with claim 12 further comprising:

delaying the received previous stage active complete signal by a first predetermined delay in order to generate the current stage active complete signal, and wherein the first predetermined delay is in addition to the processing delay.

14. The method in accordance with claim 9 further comprising:

selecting, by the self-clocked generator, one of a plurality of available clocking signals for output as the current stage active complete signal.

15. The method in accordance with claim 14 wherein selecting further comprises

receiving the plurality of available clocking signals;

receiving a configuration parameter signal operable for selecting one of the plurality of available clocking signals; and

outputting the selected clocking signal.

16. The method in accordance with claim 15 wherein each of the plurality of available clocking signals is a delayed version of the previous stage active complete signal with a predetermined delay.

17. A clock-less asynchronous processing circuit, comprising:

a plurality of processing pipelines each having a plurality of successive processing stages configured to operate asynchronously, the plurality of successive processing stages comprising,

a first asynchronous processing stage having first asynchronous logic circuitry configured to process first input data and output first processed data, a first data storage element coupled to the first asynchronous logic circuitry and configured to receive and store the first processed output data in response to a first stage active complete signal generated and output by a first self-clocked generator,

a second asynchronous processing stage having second asynchronous logic circuitry configured to process the first output processed data and output second processed data, a second data storage element coupled to the second asynchronous logic circuitry and configured to receive and store the second processed output data in response to a second stage active complete signal, and a second self-clocked generator configured to receive the first stage active complete signal, generate the second stage active complete signal in response thereto, and output the second stage active complete signal to the second data storage element, and

a third asynchronous processing stage having third asynchronous logic circuitry configured to process the second output processed data and output third processed data, a third data storage element coupled to the third asynchronous logic circuitry and configured to receive and store the third processed output data in response to a third stage active complete signal, and a third self-clocked generator configured to receive the second stage active complete signal, generate the third stage active complete signal in response thereto, and output the third stage active complete signal to the third data storage element.

18. The processing circuit in accordance with claim 17 wherein each of the second and third self-clocked generators is programmable and configured to delay the respective received first and second stage active complete signals by a predetermined delay in order to generate the respective second and third stage active complete signals.

19. A clock-less asynchronous circuit, comprising:

asynchronous logic circuitry configured to process input data and output processed data, and further configured to perform either a first processing function associated with a first processing delay or a second processing function associated with a second processing delay;

a data storage element coupled to the asynchronous logic circuitry and configured to receive and store the processed output data in response to an active complete signal; and

a self-clocked generator configured to;

receive a trigger signal,

generate and output the active complete signal after receiving the trigger signal, the active complete signal generated and output after a predetermined time period from receipt of the trigger signal, and

wherein the predetermined time period is substantially equal to or greater than the first processing delay when the asynchronous logic circuitry will perform the first processing function or the predetermined time period is substantially equal to or greater than the second processing delay when the asynchronous logic circuitry will perform the second processing function.