Multi-granular cache management in multi-processor computing environments
First Claim
1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries, the method comprising:
- identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I); and
creating a side table entry for the first cache line, the side table entry in a side table associated with the cache, the side table having a smaller number of side table entries than the number of directory entries, the side table entry associating the tag with at least one set of sub-line descriptive bits, each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line in a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode.
2 Assignments
0 Petitions
Accused Products
Abstract
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.
47 Citations
16 Claims
-
1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries, the method comprising:
-
identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I); and creating a side table entry for the first cache line, the side table entry in a side table associated with the cache, the side table having a smaller number of side table entries than the number of directory entries, the side table entry associating the tag with at least one set of sub-line descriptive bits, each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line in a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode. - View Dependent Claims (2, 3, 4)
-
-
5. A computer system for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries, the computer system comprising:
-
a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising; identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I); and creating a side table entry for the first cache line, the side table entry in a side table associated with the cache, the side table having a smaller number of side table entries than the number of directory entries, the side table entry associating the tag with at least one set of sub-line descriptive bits, each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line in a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode. - View Dependent Claims (6, 7, 8, 9, 10)
-
-
11. A computer program product for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising; identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I); and creating a side table entry for the first cache line, the side table entry in a side table associated with the cache, the side table having a smaller number of side table entries than the number of directory entries, the side table entry associating the tag with at least one set of sub-line descriptive bits, each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line in a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode. - View Dependent Claims (12, 13, 14, 15, 16)
Specification