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Tracking memory accesses when invalidating effective address to real address translations

  • US 9,740,629 B2
  • Filed: 12/19/2014
  • Issued: 08/22/2017
  • Est. Priority Date: 12/19/2014
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a memory;

    a memory management unit (MMU) having a translation lookaside buffer (TLB) configured to issue effective address to real address translation invalidation requests;

    a processor comprising;

    a bus configured to facilitate the transfer of commands and data between multiple subsystems of the processor;

    one or more coprocessors to issue memory loads and stores using effective addresses;

    an effective to real address translation (ERAT) table, wherein the ERAT table has a plurality of entries, each entry having an indicator;

    a plurality of memory access entities (MAEs) coupled to the bus, wherein the MAEs are separate from the one or more coprocessors and are configured to access effective to real address translations stored in the ERAT table to execute memory load and store operations issued by the one or more coprocessors;

    a tracking array having tracking array entries to store indexes to ERAT table entries, wherein a first tracking array entry is indexed by a first memory access entity (MAE) identifier, the first MAE identifier identifying a first MAE that uses a first effective to real address translation stored in a first ERAT table entry having its index stored in the first tracking array entry; and

    a hardware unit, separate from the one or more coprocessors and the MAEs, the hardware unit configured to;

    receive a request to execute a memory operation,determine whether the request to execute a memory operation isan address translation request issued by a second MAE to use a second effective to real address translation stored in a second ERAT table entry to translate a first effective address to a first real address oran address invalidation request issued by the MMU to invalidate a third effective to real address translation stored in a third ERAT table entry, the third ERAT table entry having a third ERAT table index,wherein the request to execute a memory operation includes the first effective address and a first process identifier, the first process identifier identifying a process associated with the first effective address;

    identify, based on the first effective address and the first process identifier, a second ERAT table index of the second ERAT entry when the request to execute a memory operation is an address translation request issued by an MAE;

    store the second ERAT table index in a second tracking array entry, wherein the second tracking array entry is indexed by a second MAE identifier identifying the second MAE;

    update a first indicator associated with the second ERAT table entry.

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