Data bus driving circuit, and semiconductor device and semiconductor memory device including the same
First Claim
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1. A data bus driving circuit comprising:
- a data processing unit that processes input data and outputs processed data;
a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and
an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.
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Abstract
Provided is a data bus driving circuit including: a data processing unit that processes input data and outputs processed data; a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.
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Citations
20 Claims
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1. A data bus driving circuit comprising:
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a data processing unit that processes input data and outputs processed data; a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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8. A semiconductor memory device, comprising:
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a memory cell array; an Error Check and Correct (ECC) decoding unit that performs error correction processing, based on an error correction code, on data read out from the memory cell array, and outputs the corrected data; a first logic inversion unit that selects, based on a determination result signal, one of the corrected data and inverted data obtained by logically inverting each value of a plurality of bits constituting the corrected data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the data that has not been corrected, and outputs the determination result signal based on a comparison result. - View Dependent Claims (9, 20)
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Specification