Efficient integrated circuits configuration data management

• US 9,740,809 B2
• Filed: 08/27/2015
• Issued: 08/22/2017
• Est. Priority Date: 08/27/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Khan, Junaid Asim, Brissenden, Scott James
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US14/837,928
• Publication Number:
  US 20170061055A1
• Time in Patent Office: 726 Days
• Field of Search: 716116, 716117
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Circuitry for efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design in an integrated circuit, a decoding circuit can retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of a decompression operation with the base configuration data to restore the configuration data. The restored configuration data can serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.

Claims

1. Configuration circuitry comprising:

a decoding circuit that receives a base configuration data set and a first data set, wherein the first data set includes compressed data differences between the base configuration data set and a decoded configuration data set, and wherein the decoding circuit comprises;

a first circuit that receives the first data set and that decompresses the first data set to create a second data set; and

a second circuit that receives the base configuration data set and the second data set from the first circuit and that outputs the decoded configuration data set using the base configuration data set and the second data set.

2. The configuration circuitry of claim 1, wherein the configuration circuitry programs a configurable circuit using the decoded configuration data set to implement a first circuit design on the configurable circuit.

3. The configuration circuitry of claim 2, wherein the first circuit receives a third data set that includes other compressed data differences between the base configuration data set and an additional decoded configuration data set, and wherein the first circuit decompresses the received third data set to create a fourth data set.

4. The configuration circuitry of claim 3, wherein the second circuit receives the base configuration data set and the fourth data set from the first circuit, wherein the second circuit restores the additional decoded configuration data set using the base configuration data set and the fourth data set.

5. The configuration circuitry of claim 4, wherein the configuration circuitry programs an additional configurable circuit with the additional decoded configuration data set to implement the first circuit design on the additional configurable circuit.

6. The configuration circuitry of claim 4, wherein the configuration circuitry programs the configurable circuit with the additional decoded configuration data set to implement a second circuit design on the configurable circuit.

7. The configurable circuitry of claim 1, wherein the first circuit further comprises:

an entropy decoding circuit that performs entropy decoding.

8. The configurable circuitry of claim 7, wherein the entropy decoding comprises a method selected from the group consisting of:

Huffman decoding, arithmetic decoding, universal decoding, and Golomb decoding.

9. The configurable circuitry of claim 1, wherein the second circuit further comprises:

a logic exclusive OR gate that performs a logic exclusive OR operation between a bit of the base configuration data set and a bit of the second data set.

10. A method for handling configuration data sets, the method comprising:

with a computer-aided design (CAD) tool, generating a base configuration data set for a base circuit design in an integrated circuit;

with the CAD tool, generating a first configuration data set corresponding to a first circuit design in the integrated circuit, wherein the first configuration data set implements the first circuit design at a first location on the integrated circuit;

comparing the first configuration data set with the base configuration data set to obtain a first configuration data difference set; and

compressing the first configuration data difference set to produce a compressed first configuration data difference set.

11. The method of claim 10, further comprising:

with the CAD tool, generating a second configuration data set using the first circuit design, wherein the second configuration data set implements the first circuit design at a second location on the integrated circuit;

comparing the second configuration data set and the base configuration data set to determine a second configuration data difference set; and

compressing the second configuration data difference set to produce a compressed second configuration data difference set.

12. The method of claim 10, wherein compressing the first configuration data difference set comprises:

performing entropy encoding of the first configuration data difference set.

13. The method of claim 12, wherein the entropy encoding is selected from the group consisting of:

Huffman encoding, arithmetic encoding, universal encoding, and Golomb encoding.

14. The method of claim 10, further comprising:

restoring the first configuration data set based on the compressed first configuration data difference set and the base configuration data set; and

programming circuitry at the first location on the integrated circuit with the restored first configuration data set to implement the first circuit design.

15. The method of claim 14, wherein restoring the first configuration data set comprises:

producing the first configuration data difference set by decompressing the compressed first configuration data difference set; and

comparing the first configuration data difference set and the base configuration data set to determine the first configuration data set.

16. The method of claim 14, further comprising:

with the CAD tool, generating a second configuration data set of a second circuit design that is different than the first circuit design;

comparing the second configuration data set and the base configuration data set to determine a second configuration data difference set; and

producing a compressed second configuration data difference set based on the second configuration data difference set.

17. The method of claim 16, further comprising:

restoring the second configuration data set based on the compressed second configuration data difference set and the base configuration data set; and

programming circuitry at the first location on the integrated circuit with the restored second configuration data set to implement the second circuit design.

18. The method of claim 10, wherein generating a first configuration data set corresponding to a first circuit design further comprises:

performing an incremental compilation of the first circuit design to generate the first configuration data set, wherein the first circuit design and the base circuit design are at least partially identical, and wherein the incremental compilation produces the first configuration data set based on at least a portion of the base configuration data set.

19. A method for generating configuration data for a configurable circuit, the method comprising:

with a computer-aided design tool, generating a first configuration data set for a first circuit design in an integrated circuit, wherein the first configuration data set implements the first circuit design at a first location on the integrated circuit;

deriving a second configuration data set from the first configuration data set, wherein the second configuration data set includes at least a portion that is identical to the first configuration data set; and

compressing the first configuration data set to produce a compressed first configuration data set and compressing the second configuration data set to produce a compressed second configuration data set.

20. The method of claim 19, wherein deriving the second configuration data set further comprises:

generating a third configuration data set for a second circuit design, wherein the third configuration data set implements the second circuit design at the first location on the integrated circuit.

21. The method of claim 20, further comprising:

comparing the third configuration data set with the first configuration data set to produce the second configuration data set, wherein the second configuration data set reflects differences between the first configuration data set and third configuration data set.

22. The method of claim 19, wherein deriving the second configuration data set further comprises:

generating a location offset between the first location on the integrated circuit and a second location on the integrated circuit.

23. The method of claim 22, further comprising:

combining the location offset with the first configuration data set to produce the second configuration data set, wherein the second configuration data set implements the first circuit design at the second location on the integrated circuit.

24. The method of claim 19, further comprising:

storing the compressed first configuration data set and the compressed second configuration data set in a storage circuit.

25. The method of claim 19, wherein compressing the first configuration data set and the second configuration data set further comprises:

using lossless encoding to produce the compressed first configuration data set.