Method of manufacturing thin-film transistor substrate

• US 9,741,588 B2
• Filed: 12/23/2014
• Issued: 08/22/2017
• Est. Priority Date: 01/10/2014
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: Kishida, Yuji, Yoshitani, Toshiaki
• Primary Examiner(s): Whalen, Daniel
• Application Number:
  US14/580,896
• Publication Number:
  US 20150200113A1
• Time in Patent Office: 973 Days
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed.

Claims

1. A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor, the method comprising:

preparing a substrate;

forming a gate electrode in a predetermined shape on the substrate;

forming a gate insulating layer on the substrate and the gate electrode, the gate insulating layer covering the gate electrode;

forming an oxide semiconductor layer in a predetermined shape on the gate insulating layer, the oxide semiconductor layer facing the gate electrode;

forming a channel protection layer on the gate insulating layer and the oxide semiconductor layer, the channel protection layer covering the oxide semiconductor layer;

removing parts of the channel protection layer to form first and second contact holes, the first and second contact holes each partially exposing the oxide semiconductor layer;

forming source and drain electrodes in predetermined shapes on the channel protection layer, the source and drain electrodes being connected to the oxide semiconductor layer via the first and second contact holes;

forming an interlayer insulating film on the channel protection layer and the source and drain electrodes, the interlayer insulating film covering the source and drain electrodes;

heating, after the interlayer insulating film is formed, the thin-film transistor substrate to increase a resistance of the oxide semiconductor layer;

removing a part of the interlayer insulating film to form a third contact hole, the third contact hole partially exposing one of the source and drain electrodes;

forming a first line layer in a predetermined shape on the interlayer insulating film, the first line layer being connected to the one of the source and drain electrodes via the third contact hole;

heating, after the first line layer is formed, the thin-film transistor substrate to decrease the resistance of the oxide semiconductor layer;

forming second, third, and fourth line layers in predetermined shapes on the first line layer;

forming a line protection layer on the interlayer insulating film and the fourth line layer, the line protection layer covering the first, second, third, and fourth line layers;

heating, after the line protection layer is formed, the thin-film transistor substrate to increase the resistance of the oxide semiconductor layer;

forming a planarization layer comprising a polyimide material on the line protection layer;

removing a part of the planarization layer to form a fourth contact hole, the fourth contact hole partially exposing the line protection layer;

heating, after removing the part of the planarization layer, the polyimide material of the planarization layer at a temperature of 250°

C. or higher to thermally cure the polyimide material;

removing a part of the line protection layer to form a fifth contact hole, the fifth contact hole being aligned with the fourth contact hole and partially exposing the fourth line layer;

heating, after the planarization layer is formed, the thin-film transistor substrate at a temperature of 240°

C. or lower, without directly exposing the oxide semiconductor layer to a heating environment; and

forming a pixel electrode on the planarization layer after the heating at the temperature of 240°

C. or lower, the pixel electrode being connected to the fourth line layer via the fourth contact hole and the fifth contact hole.

2. A thin-film transistor substrate which includes a thin-film transistor, the thin-film transistor substrate comprising:

a substrate;

a gate electrode in a predetermined shape on the substrate;

a gate insulating layer on the substrate and the gate electrode, the gate insulating layer covering the gate electrode;

an oxide semiconductor layer in a predetermined shape on the gate insulating layer, the oxide semiconductor layer facing the gate electrode;

a channel protection layer on the gate insulating layer and the oxide semiconductor layer, the channel protection layer covering the oxide semiconductor layer, the channel protection layer including first and second contact holes that each partially expose the oxide semiconductor layer;

source and drain electrodes in predetermined shapes on the channel protection layer, the source and drain electrodes being connected to the oxide semiconductor layer via the first and second contact holes;

an interlayer insulating film on the channel protection layer and the source and drain electrodes, the interlayer insulating film covering the source and drain electrodes, the interlayer insulating film including a third contact hole that partially exposes one of the source and drain electrodes;

a first line layer in a predetermined shape on the interlayer insulating film, the first line layer being connected to the one of the source and drain electrodes via the third contact hole;

second, third, and fourth line layers in predetermined shapes on the first line layer;

a line protection layer on the interlayer insulating film and the fourth line layer, the line protection layer covering the first, second, third, and fourth line layers, the line protection layer including a fourth contact hole that partially exposes the fourth line layer;

a planarization layer comprising a polyimide material on the line protection layer, the planarization layer including a fifth contact hole aligned with the fourth contact hole that partially exposes the fourth line layer; and

a pixel electrode on the planarization layer, the pixel electrode being connected to the fourth line layer via the fourth contact hole and the fifth contact hole,

wherein a resistance of the oxide semiconductor layer is increased due to a first heating process performed after the interlayer insulating film is formed and a third heating process performed after the line protection layer is formed;

the resistance of the oxide semiconductor layer is decreased due to a second heating process performed after the first line layer is formed,

the polyimide material of the planarization layer is thermally cured due to a fourth heating process performed at a temperature of 250°

C. or higher while the planarization layer is formed, and

an occurrence of a peak in a mobility curve of the thin-film transistor is suppressed due to a fifth heating process performed at a temperature of 240°

C. or lower after the planarization layer is formed, without directly exposing the oxide semiconductor layer to a heating environment.