Micro device stabilization post

• US 9,741,592 B2
• Filed: 08/22/2014
• Issued: 08/22/2017
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hu, Hsin-Hua, Bibl, Andreas, Higginson, John A.
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/466,497
• Publication Number:
  US 20140363928A1
• Time in Patent Office: 1,096 Days
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/93 Batch processes
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/40 Materials therefor

Abstract

A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Claims

1. A method of forming an array of micro devices comprising:

forming a patterned sacrificial layer including an array of openings over a device layer;

forming a stabilization layer over the patterned sacrificial layer and within the array of openings to form an array of stabilization posts over the device layer;

transferring the array of stabilization posts and the device layer to a carrier substrate; and

patterning the device layer to form a corresponding array of micro devices over the array of stabilization posts.

2. The method of claim 1, wherein transferring the array of stabilization posts and the device layer to the carrier substrate comprises bonding the stabilization layer to the carrier substrate.

3. The method of claim 2, further comprising completely removing the patterned sacrificial layer.

4. The method of claim 1, further comprising:

forming the array of openings of the patterned sacrificial layer directly over an array of conductive contacts on the device layer.

5. The method of claim 2, further comprising removing a growth substrate from the device layer after bonding the stabilization layer to the carrier substrate and prior to patterning the device layer to form the array of micro devices.

6. The method of claim 5, further comprising depositing a conductive contact layer over the device layer after removing the growth substrate.

7. The method of claim 6, further comprising annealing the conductive contact layer to form an ohmic contact with the device layer.

8. The method of claim 7, further comprising patterning the conductive contact layer to form an array of conductive contacts on the device layer directly over the array of stabilization posts.

9. The method of claim 7, further comprising annealling the conductive contact layer at a temperature of 300°

C. or greater.

10. The method of claim 2, further comprising soft-baking the stabilization layer prior to bonding the stabilization layer to the carrier substrate.

11. The method of claim 1, further comprising hard-baking the stabilization layer during or after bonding the stabilization layer to the carrier substrate.

12. A method comprising:

patterning a sacrificial layer to form an array of openings in the sacrificial layer exposing an array of conductive contacts formed on a device layer, wherein the device layer comprises;

an n-doped semiconductor layer;

a p-doped semiconductor layer; and

a quantum well layer between the n-doped semiconductor layer and the p-doped semiconductor layer;

applying a thermosetting material over the sacrificial layer and within the array of openings; and

curing the thermosetting material to solidify the thermosetting material.

13. The method of claim 12, wherein curing comprises application of UV energy.

14. The method of claim 12, wherein curing comprises application of heat.

15. The method of claim 12, wherein curing comprises achieving at least 70% cross-linking of the thermosetting material.

16. The method of claim 12, wherein the thermosetting material undergoes 10% or less volume shrinkage during curing.

17. The method of claim 12, further comprising bonding a growth substrate supporting the device layer to a carrier substrate with the cured thermosetting material.

18. The method of claim 12, further comprising patterning the sacrificial layer and an etch stop detection layer underneath the sacrificial layer to form the array of openings exposing the array of conductive contacts.

19. The method of claim 12, further comprising detecting completion of etching through the etch stop detection layer with visual observation.