Electrical connections for chip scale packaging

• US 9,741,659 B2
• Filed: 12/28/2015
• Issued: 08/22/2017
• Est. Priority Date: 10/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Liang, Shih-Wei
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US14/981,569
• Publication Number:
  US 20160111363A1
• Time in Patent Office: 603 Days
• Field of Search: 257784, 257758, 257781, 257750, 438613, 438614
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05012 in top view
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0502 Disposition
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05569 : the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05947 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/061 : Disposition
• CPC Class Codes: H01L 2224/06131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/13014 : being circular or elliptic
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Electrical connections for chip scale packaging are disclosed. In one embodiment, a semiconductor device includes a post-passivation layer disposed over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch. The semiconductor device includes a first opening through the post-passivation layer, the first opening comprising a plurality of elongated apertures. A longest of the plurality of elongated apertures comprises a first dimension, wherein the first dimension is aligned substantially perpendicular to the first direction of coefficient of thermal expansion mismatch.

Claims

1. A device comprising:

a substrate having a center region and having peripheral regions;

a conductive line on the substrate; and

a passivation layer formed on the conductive line, the passivation layer having a plurality of apertures exposing respective regions of the conductive line, a longest one of the plurality of apertures having a major axis extending in a direction along a major plane of the substrate, the direction being substantially perpendicular to a stress vector, the stress vector caused by a difference in a respective coefficients of thermal expansion between at least two materials on the substrate.

2. The device of claim 1, wherein the plurality of apertures includes a first aperture closest to the center region and having a first length, a second aperture furthest from the center region and having a second length less than the first length, and the longest one of the plurality of apertures interjacent the first and second apertures.

3. The device of claim 1, wherein the stress vector extends in a straight line from the center region to a midpoint of the longest one of the plurality of apertures.

4. The device of claim 1, wherein each aperture has a shape selected from the group consisting of an oval, an ellipse, a rectangle, and a trapezoid.

5. The device of claim 1, further comprising an undercontact metallization extending into the apertures.

6. The device of claim 1, further comprising solder connector electrically contacting the conductive line through the plurality of apertures.

7. The device of claim 1, wherein the conductive line electrically connects a contact pad underlying the conductive line to a connector overlying the conductive line.

8. The device of claim 1, wherein the conductive line extends along a major axis in a first direction and wherein the stress vector extends along the first direction.

9. The device of claim 1, wherein the conductive line comprises copper and the passivation layer comprises a material selected from the group consisting of polyimide, silicon oxide, silicon nitride, and combinations thereof.

10. A device comprising:

a plurality of device layers including a post-passivation layer, at least two of the device layers having a difference in respective coefficients of thermal expansion; and

a plurality of elongated apertures in the post-passivation layer, a longest one of the plurality of elongated apertures having a major axis extending substantially perpendicular to a first direction, the first direction corresponding to a direction of stress caused by the difference in respective coefficients of thermal expansion.

11. The device of claim 10, wherein the plurality of elongated apertures include apertures of different length along respective major axes of the plurality of elongated apertures.

12. The device of claim 10 further comprising an undercontact metallization extending atop the post-passivation layer and extending into the elongated apertures to electrically contact a post-passivation interconnect.

13. The device of claim 12, further comprising a connector extending into the plurality of elongated apertures.

14. The device of claim 10, wherein the first direction extends in a straight line from the center of the device to a midpoint of the longest one of the plurality of elongated apertures.

15. The device of claim 10, wherein each elongated aperture of the plurality of elongated apertures has a major axis extending substantially perpendicular to the first direction.

16. The device of claim 10, wherein the plurality of elongated apertures in the post-passivation layer expose a conductive line underlying the post-passivation layer.

17. The device of claim 16, wherein the conductive line extends along the first direction.

18. A method of manufacturing a semiconductor device comprising:

providing a plurality of device layers including a post-passivation layer, at least two of the device layers having a first direction of coefficient of thermal expansion mismatch;

patterning the post-passivation layer to include a first elongated aperture having a first length extending in a second direction substantially perpendicular to the first direction, and a plurality of second apertures, each second aperture having a length shorter than the first length and extending in the second direction;

lining the first elongated aperture and the plurality of second apertures with a undercontact metallization layer; and

filling the first elongated aperture and the plurality of second apertures with a conductor.

19. The method of claim 18, wherein the step of providing a plurality of device layers including a passivation layer, at least two of the device layers having a first direction of coefficient of thermal expansion mismatch includes:

forming a plurality of metallization layers over a substrate;

forming a contact pad over a topmost one of the plurality of metallization layers;

forming a first passivation layer over the plurality of metallization layers and the contact pad;

patterning the first passivation layer to form an opening exposing the contact pad;

forming a patterned second passivation layer over the opening exposing the contact pad; and

forming an interconnect on the patterned second passivation layer and in electrical contact with the contact pad.

20. The method of claim 18, wherein the first direction of coefficient of thermal expansion mismatch extends along a top major surface of the semiconductor device in a line from a center of the top major surface to the periphery of the top major surface of the semiconductor device.