Logic semiconductor devices

• US 9,741,661 B2
• Filed: 06/21/2016
• Issued: 08/22/2017
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Azmat, Raheel, Rwik, Sengupta, Kim, Su-Hyeon, Park, Chul-Hong, Lim, Jae-Hyoung
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US15/188,743
• Publication Number:
  US 20170117223A1
• Time in Patent Office: 427 Days
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Claims

1. A logic semiconductor device, comprising:

a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction;

an isolation layer defining the active patterns;

a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction;

a plurality of lower wirings extending in the horizontal direction over the gate patterns;

a plurality of upper wirings extending in the vertical direction over the lower wirings; and

a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

2. The logic semiconductor device of claim 1, further comprising a gate contact on the gate pattern.

3. The logic semiconductor device of claim 2, wherein the through contact directly contacts the bottom surface of the upper wiring and the top surface of the gate contact.

4. The logic semiconductor device of claim 2, further comprising an active contact electrically connected to an upper portion of the active patterns adjacent to the gate patterns.

5. The logic semiconductor device of claim 4, wherein top surfaces of the active contact and the gate contact relative to the active patterns are coplanar with each other.

6. The logic semiconductor device of claim 4, wherein the active contact is electrically connected to one of the lower wirings.

7. The logic semiconductor device of claim 4, further comprising:

a first contact connecting the active contact and one of the lower wirings; and

a second contact connecting at least one of the lower wirings and at least one of the upper wirings.

8. The logic semiconductor device of claim 1, wherein each of the upper wirings overlaps each of the gate patterns.

9. The logic semiconductor device of claim 8, wherein the lower wirings overlap the active patterns.

10. The logic semiconductor device of claim 9, wherein the lower wirings do not overlap a portion of the isolation layer between the active patterns.

11. A logic semiconductor device, comprising:

a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction;

an isolation layer defining the active patterns;

a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction;

a plurality of lower wirings extending in the horizontal direction over the gate patterns;

an insulation black dividing at least one lower wiring of the lower wirings into a plurality of fragments; and

a plurality of upper wirings extending in the vertical direction over the lower wirings.

12. The logic semiconductor device of claim 11, wherein the logic semiconductor device comprises a first region, a second region and a third region,

wherein the active patterns are disposed in the first region and the third region, and a portion of the isolation layer between the active patterns is exposed in the second region,

wherein the lower wirings comprise a first lower wiring, a second lower wiring and a third lower wiring disposed in the first region, the second region and the third region, respectively.

13. The logic semiconductor device of claim 12, wherein the first lower wiring is one of a plurality of first lower wirings and the third lower wiring is one of a plurality of third lower wirings and wherein the plurality of the first lower wirings or the plurality of the third lower wirings is disposed in the first region or the third region, respectively, and

the second lower wiring comprises a single second lower wiring in the second region.

14. The logic semiconductor device of claim 13, wherein the second lower wiring has a width greater than a width of each of the first lower wiring and the third lower wiring.

15. The logic semiconductor device of claim 12, wherein the at least one lower wiring comprises the second lower wiring.

16. The logic semiconductor device of claim 15, wherein the insulation block comprises:

a first insulation block dividing the second lower wiring; and

a second insulation block confining the lower wirings and being commonly provided at peripheral portions of the first region, the second region and the third region.

17. The logic semiconductor device of claim 16, wherein the second lower wiring is one of a plurality of second lower wirings and the first insulation block is one of a plurality of first insulation blocks, which are disposed in the second region,

wherein the first insulation blocks are arranged in a staggered configuration in a plan view.

18. The logic semiconductor device of claim 12, wherein the lower wirings further comprise a fourth lower wiring disposed at a peripheral portion in the vertical direction of the logic semiconductor device,

wherein the fourth lower wiring serves as a power rail.

19. A logic semiconductor device, comprising:

an active pattern;

a gate pattern on the active pattern;

an upper wiring aligned with the gate pattern and extending in a first direction; and

a lower wiring between the gate pattern and the upper wiring and being aligned with the active pattern so as to extend in a second direction, the upper wiring crossing over the lower wiring;

wherein edges of the upper wiring are substantially straight without deviating from the first direction; and

wherein edges of the lower wiring are substantially straight without deviating from the second direction.