Three-dimensional 3D-oP-based package

• US 9,741,697 B2
• Filed: 12/15/2016
• Issued: 08/22/2017
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US15/381,073
• Publication Number:
  US 20170098632A1
• Time in Patent Office: 250 Days
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H10B 20/10 : ROM devices comprising bipolar components
• CPC Class Codes: H10B 20/25 : One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM

Abstract

The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D²-oP). The mask-patterns for different dice in a same 3D²-oP package are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different dice in a same 3D²-oP package.

Claims

1. A three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D²-oP), comprising a first 3D-oP die and a second 3D-oP die with said second 3D-oP die stacked above said first 3D-oP die, wherein:

said first 3D-oP die comprises first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array;

said second 3D-oP die comprises third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said third data-coding layer storing a third data-array and said fourth data-coding layer storing a fourth data-array;

wherein all 3D2-oP packages in a same 3D2-oP batch have a same data-array set; and

at least two 3D2-oP packages in said batch have different data-array sequences.

2. The 3D²-oP according to claim 1, wherein said first 3D-oP die comprises first and second memory levels with said second memory level located above said first memory level, said first memory level comprising said first data-coding layer and said second memory level comprising said second data-coding layer.

3. The 3D²-oP according to claim 2, wherein said first 3D-oP die further comprises a first configurable-input for configuring the input of said first 3D-oP die based on the data-array sequence in said first 3D-oP die.

4. The 3D²-oP according to claim 1, wherein said second 3D-oP die comprises a third memory level and a fourth memory level above said third memory level, said third memory level comprising said third data-coding layer and said fourth memory level comprising said fourth data-coding layer.

5. The 3D²-oP according to claim 4, wherein said second 3D-oP die further comprises a second configurable-input for configuring the input of said second 3D-oP die based on the data-array sequence in said second 3D-oP die.

6. The 3D²-oP according to claim 1, wherein said first 3D-oP die comprises a first memory level having said first and second data-coding layers.

7. The 3D²-oP according to claim 6, wherein said first 3D-oP die further comprises a first configurable-output for configuring the output of said first 3D-oP die based on the data-array sequence in said first 3D-oP die.

8. The 3D²-oP according to claim 7, wherein said second 3D-oP die comprises a second memory level having said third and fourth data-coding layers.

9. The 3D²-oP according to claim 8, wherein said second 3D-oP die further comprises a second configurable-output for configuring the output of said second 3D-oP die based on the data-array sequence in said second 3D-oP die.

10. A batch of three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D²-oP), comprising first and second 3D²-oP packages, wherein:

said first 3D2-oP package comprises at least a first 3D-oP die and a second 3D-oP die with said second 3D-oP die stacked above said first 3D-oP die, wherein;

said first 3D-oP die comprising first and second data-coding layers with said second data-coding layer located above said first data-coding layer, said first data-coding layer storing a first data-array and said second data-coding layer storing a second data-array; and

said second 3D-oP die comprising third and fourth data-coding layers with said fourth data-coding layer located above said third data-coding layer, said third data-coding layer storing a third data-array and said fourth data-coding layer storing a fourth data-array;

said second 3D2-oP package comprises at least a third 3D-oP die and a fourth 3D-oP die with said fourth 3D-oP die stacked above said third 3D-oP die, wherein;

said third 3D-oP die comprising fifth and sixth data-coding layers with said sixth data-coding layer located above said fifth data-coding layer, said fifth data-coding layer storing said second data-array and said sixth data-coding layer storing said first data-array; and

said fourth 3D-oP die comprising seventh and eighth data-coding layers with said eighth data-coding layer located above said seventh data-coding layer, said seventh data-coding layer storing said fourth data-array and said eighth data-coding layer storing said third data-array.

11. The 3D²-oP batch according to claim 10, wherein:

said first 3D-oP die comprises first and second memory levels with said second memory level located above said first memory level, said first memory level comprising said first data-coding layer and said second memory level comprising said second data-coding layer;

said third 3D-oP die comprises fifth and sixth memory levels with said sixth memory level located above said fifth memory level, said fifth memory level comprising said fifth data-coding layer and said sixth memory level comprising said sixth data-coding layer.

12. The 3D²-oP batch according to claim 11, wherein said first or third 3D-oP die further comprises a configurable-input for configuring the input of said 3D-oP die based on the data-array sequence.

13. The 3D²-oP batch according to claim 10, wherein:

said second 3D-oP die comprises third and fourth memory levels with said fourth memory level located above said third memory level, said third memory level comprising said third data-coding layer and said fourth memory level comprising said fourth data-coding layer;

said fourth 3D-oP die comprises seventh and eighth memory levels with said eighth memory level located above said seventh memory level, said seventh memory level comprising said seventh data-coding layer and said eighth memory level comprising said eighth data-coding layer.

14. The batch of 3D²-oP according to claim 13, wherein said third or fourth 3D-oP die further comprises a configurable-input for configuring the input of said 3D-oP die based on the data-array sequence.

15. The 3D²-oP batch according to claim 10, wherein:

said first 3D-oP die comprises a first memory level, said first memory level comprising said first and second data-coding layers;

said third 3D-oP die comprises a third memory level, said third memory level comprising said fifth and sixth data-coding layers.

16. The batch of 3D²-oP according to claim 15, wherein said first or third 3D-oP die further comprises a configurable-output for configuring the output of said 3D-oP die based on the data-array sequence.

17. The 3D²-oP batch according to claim 10, wherein:

said second 3D-oP die comprises a second memory level, said second memory level comprising said third and fourth data-coding layers;

said fourth 3D-oP die comprises a fourth memory level, said fourth memory level comprising said seventh and eighth data-coding layers.

18. The batch of 3D²-oP according to claim 17, wherein said second or fourth 3D-oP die further comprises a configurable-output for configuring the output of said 3D-oP die based on the data-array sequence.