Cascode semiconductor device structure and method therefor

• US 9,741,711 B2
• Filed: 09/14/2015
• Issued: 08/22/2017
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Venkatraman, Prasad, Hossain, Zia, Liu, Chun-Li, Jeon, Woochul, McDonald, Jason
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US14/853,729
• Publication Number:
  US 20160118379A1
• Time in Patent Office: 708 Days
• Field of Search: 257192, 257368, 257195, 257E29317, 257500, 257565, 438172
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and an opposing second major surface;

a heterostructure adjacent the first major surface, the heterostructure comprising;

a channel layer; and

a barrier layer over the channel layer;

a first electrode disposed proximate to a first portion of the channel layer;

a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;

a third electrode disposed on the second major surface of the semiconductor substrate;

a control electrode disposed between the first electrode and the second electrode and configured to control a first current path between the first electrode and the second electrode;

a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically connected to the first electrode; and

a rectifier device disposed in the semiconductor substrate and electrically connected to the first trench electrode and electrically connected to the third electrode, but not electrically connected to the second electrode, wherein the rectifier device is configured to provide a second current path generally perpendicular to the first current path, and wherein the control electrode is electrically connected to the third electrode through the semiconductor substrate to provide the semiconductor device as a two-terminal device.

2. The semiconductor device of claim 1 further comprising a second trench electrode electrically connecting the control electrode to the third electrode through the semiconductor substrate, wherein the second trench electrode comprises a trench and a conductive material in the trench.

3. The semiconductor device of claim 2, wherein the second trench electrode comprises a dielectric layer between sidewall surfaces of the trench and the conductive material.

4. The semiconductor device of claim 1, wherein the rectifier device comprises a first doped region having a first conductivity type and adjoining a lower surface of the first trench electrode, and wherein the semiconductor substrate comprises:

a semiconductor region adjacent the first doped region and comprising a second conductivity type opposite to the first conductivity type; and

a second doped region having the second conductivity type and adjoining the second major surface, wherein the second doped region has a higher dopant concentration than the semiconductor region, and wherein the first doped region is interposed between at least a portion of the semiconductor region and the second doped region such that the semiconductor region separates the first doped region from the heterostructure.

5. The semiconductor device of claim 4 further comprising a third doped region of the second conductivity type disposed between the semiconductor region and the heterostructure.

6. The semiconductor device of claim 4, wherein the first doped region laterally extends to overlap the first control electrode.

7. The semiconductor device of claim 1, wherein:

the channel layer comprises a group III-V material;

the barrier layer comprises a group III-V material; and

the first electrode overlaps the first trench electrode.

8. The semiconductor device of claim 1, wherein the first electrode comprises a pad portion having a first part and a second part, and wherein the first part is between the first control electrode and the second part, and wherein the second part overlaps the first trench electrode.

9. The semiconductor device of claim 8, wherein the pad portion comprises a third part connecting the first part to the second part, and wherein a portion of the heterostructure is laterally between the first part and the second part.

10. The semiconductor device of claim 1, wherein the first trench electrode comprises a trench and a conductive material disposed overlying the trench.

11. The semiconductor device of claim 10, wherein the first trench electrode further comprises a dielectric layer between sidewall surfaces of the trench and the conductive material.