Three-dimensional semiconductor memory devices
First Claim
1. A three-dimensional semiconductor memory device comprising:
- a semiconductor pattern disposed on a semiconductor substrate, wherein the semiconductor pattern comprises an opening, a first impurity region having a first conductivity type and a second impurity region having a second conductivity type that is different from the first conductivity type, and wherein the semiconductor pattern further comprises a body contact impurity region that has the first conductivity type and has an impurity concentration higher than an impurity concentration of the first impurity region;
a peripheral transistor disposed between the semiconductor substrate and the semiconductor pattern;
a first peripheral interconnection structure disposed between the semiconductor substrate and the semiconductor pattern and electrically connected to the peripheral transistor;
memory cell gate conductive patterns disposed on the semiconductor pattern;
memory cell vertical structures extending through respective ones of the memory cell gate conductive patterns and being connected to the semiconductor pattern;
memory cell bit line contact plugs disposed on respective ones of the memory cell vertical structures;
a bit line disposed on the memory cell bit line contact plugs; and
a peripheral bit line contact structure being disposed between the bit line and the first peripheral interconnection structure and extending through the opening of the semiconductor pattern.
1 Assignment
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Accused Products
Abstract
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.
42 Citations
17 Claims
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1. A three-dimensional semiconductor memory device comprising:
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a semiconductor pattern disposed on a semiconductor substrate, wherein the semiconductor pattern comprises an opening, a first impurity region having a first conductivity type and a second impurity region having a second conductivity type that is different from the first conductivity type, and wherein the semiconductor pattern further comprises a body contact impurity region that has the first conductivity type and has an impurity concentration higher than an impurity concentration of the first impurity region; a peripheral transistor disposed between the semiconductor substrate and the semiconductor pattern; a first peripheral interconnection structure disposed between the semiconductor substrate and the semiconductor pattern and electrically connected to the peripheral transistor; memory cell gate conductive patterns disposed on the semiconductor pattern; memory cell vertical structures extending through respective ones of the memory cell gate conductive patterns and being connected to the semiconductor pattern; memory cell bit line contact plugs disposed on respective ones of the memory cell vertical structures; a bit line disposed on the memory cell bit line contact plugs; and a peripheral bit line contact structure being disposed between the bit line and the first peripheral interconnection structure and extending through the opening of the semiconductor pattern. - View Dependent Claims (2, 3)
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4. A three-dimensional semiconductor memory device comprising:
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a semiconductor pattern disposed on a semiconductor substrate; a peripheral transistor disposed between the semiconductor substrate and the semiconductor pattern; a peripheral interconnection structure disposed between the semiconductor substrate and the semiconductor pattern, wherein the peripheral interconnection structure is electrically connected to the peripheral transistor and comprises a peripheral contact pad; a gate conductive structure disposed on the semiconductor pattern, wherein the gate conductive structure comprises a plurality of memory cell gate conductive patterns stacked in a direction perpendicular to the semiconductor pattern; a memory cell vertical structure extending through the gate conductive structure; a memory cell conductive line disposed on the memory cell vertical structure, wherein the memory cell conductive line has a length smaller than a width of the semiconductor pattern; a peripheral contact structure disposed between the memory cell conductive line and the peripheral contact pad; and a lower interlayer insulating layer on the semiconductor substrate and a buffer insulating layer disposed between the lower interlayer insulating layer and the semiconductor pattern. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A three-dimensional semiconductor memory device comprising:
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a substrate; a bit line on the substrate, the bit line extending in a first direction; first and second semiconductor patterns between the substrate and the bit line, the first and second semiconductor patterns being spaced apart from each other in the first direction by a gap therebetween and lower surfaces of the first and second semiconductor patterns being coplanar; first and second gate structures between an upper surface of the first semiconductor pattern and the bit line, the first and second gate structures being disposed along the first direction; a first memory cell vertical structure extending through the first gate structure and a second memory cell vertical structure extending through the second gate structure, each of the first and second memory cell vertical structures comprising a channel layer and both the first and second memory cell vertical structures extending away from the upper surface of the first semiconductor pattern and being connected to the bit line; an insulating layer between the substrate and the first and second semiconductor patterns; a conductive contact pad in the insulating layer; and a bit line contact structure extending through the gap between the first and second semiconductor patterns and extending away from an upper surface of the substrate, an upper portion of the bit line contact structure contacting the bit line and a lower portion of the bit line contact structure contacting the conductive contact pad, wherein the first and second semiconductor patterns comprise portions of a same semiconductor pattern, and the gap comprises a portion of an opening in the semiconductor pattern, wherein the opening has a line shape extending in a second direction different from the first direction when viewed from a plan perspective, and wherein the bit line contact structure comprises one of a plurality of bit line of contact structures, and ones of the plurality of bit line contact structures are disposed along the second direction and extend through the opening. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification