Array substrate fabricating method

• US 9,741,751 B2
• Filed: 04/16/2015
• Issued: 08/22/2017
• Est. Priority Date: 11/06/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Wang, Ke, Yoo, Seongyeol
• Primary Examiner(s): Geyer, Scott B
• Assistant Examiner(s): IMTIAZ, S M SOHEL
• Application Number:
  US14/778,257
• Publication Number:
  US 20160284741A1
• Time in Patent Office: 859 Days
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor material layer and a first photoresist layer on a substrate successively, forming a pattern of an active layer comprising thin film transistors by using the semiconductor material layer and the first photoresist layer through photoetching technology, and reserving the first photoresist layer at least on conductive areas of the active layer when the thin film transistors are turned on; and forming a first material layer on the substrate on which the active layer is formed and the first photoresist layer is reserved on the active layer, and forming a pattern comprising first structures by using the first material layer through the photoetching technology. The method is adapted for fabricating an array substrate using metal oxide thin film transistors.

Claims

1. An array substrate fabricating method, comprising:

step S1, forming a semiconductor material layer and a first photoresist layer on a substrate successively, forming a pattern of an active layer comprising thin film transistors by using the semiconductor material layer and the first photoresist layer through photoetching technology, and reserving the first photoresist layer at least on conductive areas of the active layer when the thin film transistors are turned on; and

step S2, forming a first material layer on the substrate on which the active layer is formed and the first photoresist layer is reserved on the active layer, and forming a pattern comprising first structures by using the first material layer through the photoetching technology.

2. The array substrate fabricating method according to claim 1, wherein

the first material layer is a transparent conductive material layer;

the first structures are pixel electrodes or common electrodes.

3. The array substrate fabricating method according to claim 2, wherein

prior to the step S1, the method further comprises:

forming a pattern comprising sources and drains on the substrate through a patterning process,

the first photoresist layer reserved in the step S1 overlaps with the active layer.

4. The array substrate fabricating method according to claim 3, wherein prior to the step of forming a pattern comprising sources and drains through a patterning process, the method further comprises:

forming a pattern comprising gates and gate lines on the substrate through the patterning process; and

forming a gate insulating layer on the substrate on which the preceding steps are accomplished.

5. The array substrate fabricating method according to claim 2, wherein the step S2 comprises:

step S21, forming a transparent conductive material layer and a second photoresist layer successively on the substrate on which the preceding steps are accomplished;

step S22, forming a pattern comprising pixel electrodes or common electrodes by using the transparent conductive material layer through the photoetching technology; and

step S23, stripping the first photoresist layer and the second photoresist layer.

6. The array substrate fabricating method according to claim 1, wherein

the first material layer is a metal layer;

the first structures are sources and drains.

7. The array substrate fabricating method according to claim 6, wherein the first photoresist layer reserved in the step S1 is located on conductive areas of the active layer when the thin film transistors are turned on, the first photoresist layer is not reserved on the areas of the active layer in contact with the sources and the drains.

8. The array substrate fabricating method according to claim 7, wherein the step S1 comprises:

step S11, forming a semiconductor material layer and a first photoresist layer on a substrate successively;

step S12, exposing and developing the first photoresist layer through gradient exposure process, such that the first photoresist layer of a first thickness is reserved at positions corresponding to the areas of the active layer in contact with the sources and the drains, the first photoresist layer of a second thickness is reserved at positions corresponding to the conductive areas of the active layer when the thin film transistors are turned on, and the first photoresist layer is not reserved at other positions, the first thickness is less than the second thickness; and

step S13, removing the semiconductor material layer not covered by the first photoresist layer, so as to form a pattern comprising the active layer, and thinning the reserved first photoresist layer, such that the first photoresist layer of the first thickness is removed, the first photoresist layer of the second thickness is thinned, and reserving the first photoresist layer on the conductive areas of the active layer when the thin film transistors are turned on.

9. The array substrate fabricating method according to claim 7, wherein the step S2 comprises:

step S21, forming a metal layer and a second photoresist layer successively on the substrate on which the preceding steps are accomplished;

step S22, forming a pattern comprising sources and drains by using the metal layer through the photoetching technology; and

step S23, removing the second photoresist layer and the first photoresist layer.

10. The array substrate fabricating method according to claim 6, wherein prior to the step S1, the method further comprises:

forming a pattern comprising gates and gate lines on the substrate through the patterning process; and

forming a gate insulating layer on the substrate on which the preceding steps are accomplished.

11. The array substrate fabricating method according to claim 1, wherein

the semiconductor material layer is a metal oxide semiconductor material layer.

12. The array substrate fabricating method according to claim 11, wherein

the first material layer is a transparent conductive material layer;

the first structures are pixel electrodes or common electrodes.

13. The array substrate fabricating method according to claim 12, wherein

prior to the step S1, the method further comprises:

forming a pattern comprising sources and drains on the substrate through a patterning process,

the first photoresist layer reserved in the step S1 overlaps with the active layer.

14. The array substrate fabricating method according to claim 13, wherein prior to the step of forming a pattern comprising sources and drains through a patterning process, the method further comprises:

forming a pattern comprising gates and gate lines on the substrate through the patterning process; and

forming a gate insulating layer on the substrate on which the preceding steps are accomplished.

15. The array substrate fabricating method according to claim 12, wherein the step S2 comprises:

step S21, forming a transparent conductive material layer and a second photoresist layer successively on the substrate on which the preceding steps are accomplished;

step S22, forming a pattern comprising pixel electrodes or common electrodes by using the transparent conductive material layer through the photoetching technology; and

step S23, stripping the first photoresist layer and the second photoresist layer.

16. The array substrate fabricating method according to claim 11, wherein

the first material layer is a metal layer;

the first structures are sources and drains.

17. The array substrate fabricating method according to claim 16, wherein the first photoresist layer reserved in the step S1 is located on conductive areas of the active layer when the thin film transistors are turned on, the first photoresist layer is not reserved on the areas of the active layer in contact with the sources and the drains.

18. The array substrate fabricating method according to claim 17, wherein the step S1 comprises:

step S11, forming a semiconductor material layer and a first photoresist layer on a substrate successively;

step S12, exposing and developing the first photoresist layer through gradient exposure process, such that the first photoresist layer of a first thickness is reserved at positions corresponding to the areas of the active layer in contact with the sources and the drains, the first photoresist layer of a second thickness is reserved at positions corresponding to the conductive areas of the active layer when the thin film transistors are turned on, and the first photoresist layer is not reserved at other positions, the first thickness is less than the second thickness; and

step S13, removing the semiconductor material layer not covered by the first photoresist layer, so as to form a pattern comprising the active layer, and thinning the reserved first photoresist layer, such that the first photoresist layer of the first thickness is removed, the first photoresist layer of the second thickness is thinned, and reserving the first photoresist layer on the conductive areas of the active layer when the thin film transistors are turned on.

19. The array substrate fabricating method according to claim 17, wherein the step S2 comprises:

step S21, forming a metal layer and a second photoresist layer successively on the substrate on which the preceding steps are accomplished;

step S22, forming a pattern comprising sources and drains by using the metal layer through the photoetching technology; and

step S23, removing the second photoresist layer and the first photoresist layer.

20. The array substrate fabricating method according to claim 16, wherein prior to the step S1, the method further comprises:

forming a pattern comprising gates and gate lines on the substrate through the patterning process; and

forming a gate insulating layer on the substrate on which the preceding steps are accomplished.