Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

• US 9,741,803 B2
• Filed: 06/22/2016
• Issued: 08/22/2017
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Levy, Sagy, Jenne, Fredrick, Ramkumar, Krishnaswamy
• Primary Examiner(s): YUSHINA, GALINA G
• Application Number:
  US15/189,547
• Publication Number:
  US 20160308009A1
• Time in Patent Office: 426 Days
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

A charge trap memory device is provided. In one embodiment, the charge trap memory device includes a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region. A tunnel dielectric layer is disposed on the vertical channel, a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed on the first nitride layer. The second nitride layer includes a majority of charge traps distributed in the multi-layer charge-trapping region.

Claims

1. A charge trap memory device comprising:

a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region;

a tunnel dielectric layer disposed surrounding at least partially the vertical channel; and

a multi-layer charge-trapping region including a first deuterated layer disposed abutting the tunnel dielectric layer, a first nitride layer disposed abutting the first deuterated layer, and a second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed abutting the first nitride layer,

wherein the second nitride layer comprises a majority of charge traps distributed in the multi-layer charge-trapping region.

2. The memory device of claim 1 wherein the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.

3. The memory device of claim 1 wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

4. The memory device of claim 1 wherein the first deuterated layer and the first nitride layer comprise a deuterated derivative and a non-deuterated derivative of a same material respectively.

5. The memory device of claim 4 wherein the first nitride layer is deuterated, and wherein a concentration of deuterium in the first nitride layer is less than a concentration of deuterium in the first deuterated layer.

6. The memory device of claim 5 wherein there is a gradient of deuterium atom concentration from a high concentration of deuterium in the first deuterated layer to a low concentration of deuterium in the first nitride layer.

7. The memory device of claim 1 wherein the vertical channel comprises recrystallized polysilicon.

8. The memory device of claim 1 wherein the multi-layer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

9. A charge trap memory device comprising:

a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region;

a tunnel dielectric layer disposed surrounding at least partially the vertical channel; and

a multi-layer charge-trapping region including a first deuterated layer disposed abutting the tunnel dielectric layer, a first nitride layer disposed abutting the first deuterated layer, a second nitride layer disposed abutting the first nitride layer, and a second deuterated layer disposed abutting the second nitride layer,

wherein the first nitride layer comprises a substantially trap-free oxygen-rich nitride layer.

10. The memory device of claim 9 wherein the second nitride layer comprises a deuterium-free trap-dense, oxygen-lean nitride.

11. The memory device of claim 9 wherein the second nitride layer comprises a majority of charge traps distributed in the multi-layer charge-trapping region.

12. The memory device of claim 9 wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

13. The memory device of claim 9 wherein the first nitride layer is deuterated, and wherein a concentration of deuterium in the first nitride layer is less than a concentration of deuterium in the first deuterated layer.

14. The memory device of claim 13 wherein there is a gradient of deuterium atom concentration from a high concentration of deuterium in the first deuterated layer to a low concentration of deuterium in the first nitride layer.

15. The memory device of claim 9 wherein the multi-layer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

16. A charge trap memory device comprising:

a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region;

a tunnel dielectric layer disposed surrounding at least partially the vertical channel; and

a multi-layer charge-trapping region including a first deuterated layer disposed abutting the tunnel dielectric layer, a first nitride layer disposed abutting the first deuterated layer, a second nitride layer disposed abutting the first nitride layer, and a second deuterated layer disposed abutting the second nitride layer,

wherein the second deuterated layer has a concentration of deuterium lower than a concentration of deuterium in the first deuterated layer.

17. The memory device of claim 16 wherein the second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed on the first nitride layer.

18. The memory device of claim 16 wherein the second nitride layer comprises a majority of charge traps distributed in the multi-layer charge-trapping region.

19. The memory device of claim 16 wherein the first nitride layer is deuterated, and wherein a concentration of deuterium in the first nitride layer is less than a concentration of deuterium in the first deuterated layer.

20. The memory device of claim 19 wherein there is a gradient of deuterium atom concentration from a high concentration of deuterium in the first deuterated layer to a low concentration of deuterium in the first nitride layer.