Nonplanar device with thinned lower body portion and method of fabrication

• US 9,741,809 B2
• Filed: 09/16/2015
• Issued: 08/22/2017
• Est. Priority Date: 10/25/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Doyle, Brian S., Brask, Justin K., Chau, Robert S., Letson, Thomas A.
• Primary Examiner(s): Movva, Amar
• Application Number:
  US14/856,490
• Publication Number:
  US 20160005829A1
• Time in Patent Office: 706 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A nonplanar transistor, comprising:

a semiconductor body disposed above a substrate, the semiconductor body having a channel region comprising;

a top surface; and

a pair of laterally opposite sidewalls extending downward from the top surface;

an uppermost body portion adjacent the top surface and above a lowermost body portion, wherein a widest width of the uppermost body portion is located where the uppermost body portion meets the lowermost body portion, and wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward downward from the uppermost body portion;

a gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the channel region including on and in direct contact with the laterally opposite sidewalls of the lowermost body portion which continually taper inward;

a gate electrode formed on the gate dielectric layer on the top surface and sidewalls of the channel region; and

a pair of source/drain regions on opposite sides of the channel region.

2. The nonplanar transistor of claim 1, wherein the channel region is disposed on an insulating layer disposed on the substrate.

3. The nonplanar transistor of claim 1, wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward to meet at a substantially flat bottom surface of the channel region.

4. The nonplanar transistor of claim 1, wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward to meet at a point.

5. The nonplanar transistor of claim 1, wherein a distance between the sidewalls at a bottom of the lowermost body portion is sufficiently small so as to improve the short channel effects of the transistor.

6. The nonplanar transistor of claim 1, wherein the semiconductor body comprises silicon.

7. The nonplanar transistor of claim 1, wherein the composition of the gate dielectric layer formed on the top surface is the same composition as the gate dielectric layer formed on the sidewalls.

8. The nonplanar transistor of claim 1, wherein the gate dielectric layer is a continuous gate dielectric layer formed on and in direct contact with the top surface and the sidewalls of the channel region.

9. A method of fabricating a nonplanar transistor, the method comprising:

forming a semiconductor body above a substrate, the semiconductor body having a channel region comprising;

a top surface; and

a pair of laterally opposite sidewalls extending downward from the top surface;

an uppermost body portion adjacent the top surface and above a lowermost body portion, wherein a widest width of the uppermost body portion is located where the uppermost body portion meets the lowermost body portion, and wherein the laterally opposite sidewalls of the lowermost body portion taper continually inward downward from the uppermost body portion;

forming a gate dielectric layer on and in direct contact with the top surface and the sidewalls of the channel region including on and in direct contact with the laterally opposite sidewalls of the lowermost body portion which continually taper inward;

forming a gate electrode on the gate dielectric layer on the top surface and sidewalls of the channel region; and

forming a pair of source/drain regions on opposite sides of the channel region.

10. The method of claim 9, wherein forming the semiconductor body comprises forming the channel region on an insulating layer.

11. The method of claim 9, wherein forming the semiconductor body comprises forming a silicon body.

12. The method of claim 9, wherein forming the gate dielectric layer comprises forming a same composition gate dielectric layer on the top surface and on the sidewalls.

13. The method of claim 9, wherein forming the gate dielectric layer comprises forming a continuous gate dielectric layer on and in direct contact with the top surface and the sidewalls of the channel region.