Semiconductor device and manufacturing method thereof

• US 9,741,829 B2
• Filed: 05/15/2015
• Issued: 08/22/2017
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Cheng-Yi, Yeh, Chih Chieh, Chang, Chih-Sheng, Chiang, Hung-Li, Chen, Hung-Ming, Yeo, Yee-Chia
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US14/714,227
• Publication Number:
  US 20160336429A1
• Time in Patent Office: 830 Days
• Field of Search: 257401
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Claims

1. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming a source/drain structure in the fin structure;

after forming the source/drain structure in the fin structure, forming a gate structure over a part of the fin structure, the gate structure extending in a second direction perpendicular to the first direction;

forming an interlayer dielectric layer over the fin structure, the source/drain structure and the gate structure;

forming a contact hole in the interlayer dielectric layer so as to expose the source/drain structure;

directly depositing a cap layer including silicon phosphide, by using a silicon containing gas and a phosphorous containing gas, on a bottom surface and sidewalls of the contact hole and on an entire upper surface of the interlayer dielectric layer; and

forming a contact metal layer over the cap layer.

2. The method of claim 1, further comprising forming a silicide layer between the cap layer and the contact metal layer.

3. The method of claim 1, further comprising:

between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

4. The method of claim 3, wherein:

the fin structure is made of germanium or germanium compound, and

the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

5. The method of claim 1, wherein:

the fin structure is made of germanium or germanium compound.

6. The method of claim 1, wherein the source/drain structure includes germanium phosphide.

7. The method of claim 1, wherein:

the contact hole is formed in the interlayer dielectric layer while maintaining coverage of a top surface of a metal electrode of the gate structure by the interlayer dielectric layer.

8. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming a fin structure over a substrate, the fin structure extending in a first direction and including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming a dummy gate structure over a part of the fin structure, the dummy gate structure extending in a second direction crossing the first direction;

recessing the fin structure not covered by the dummy gate structure;

forming a source/drain structure in the recessed fin structure;

forming an insulating layer over the dummy gate structure and the source/drain structure;

removing the dummy gate structure, thereby forming a gate space;

after forming the source/drain structure in the recessed fin structure and after removing the dummy gate structure, forming a metal gate structure in the gate space;

forming a contact hole in the insulating layer so as to expose the source/drain structure;

directly depositing a cap layer including silicon phosphide, by using a silicon containing gas and a phosphorous containing gas, on a bottom surface and sidewalls of the contact hole and on an entire upper surface of the insulating layer; and

forming a contact metal layer over the cap layer.

9. The method of claim 8, further comprising forming a silicide layer between the cap layer and the contact metal layer.

10. The method of claim 8, further comprising:

between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

11. The method of claim 10, wherein:

the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

12. The method of claim 8, wherein:

the fin structure is made of germanium or germanium compound.

13. The method of claim 8, wherein the source/drain structure includes germanium phosphide.

14. The method of claim 8, wherein:

the contact hole is formed in the insulating layer so as to expose the source/drain structure, while maintaining coverage of a top surface of the metal gate structure by the insulating layer.

15. A method of manufacturing a semiconductor device including a Fin FET, the method comprising:

forming plural fin structures over a substrate, the fin structures extending in a first direction, each of the fin structures including an upper layer, a part of the upper layer being exposed from an isolation insulating layer;

forming source/drain structures in the fin structures, respectively;

after forming the source/drain structures in the fin structures, forming one or more gate structures over a part of the fin structures, the one or more gate structures extending in a second direction perpendicular to the first direction;

forming an interlayer dielectric layer over the fin structures and the source/drain structures;

forming a contact hole in the interlayer dielectric layer so as to expose the source/drain structures;

directly depositing a cap layer including silicon phosphide, by using a silicon containing gas and a phosphorous containing gas, on a bottom surface and sidewalls of the contact hole and on an entire upper surface of the interlayer dielectric layer; and

forming a contact metal layer over the cap layer.

16. The method of claim 15, further comprising forming a silicide layer between the cap layer and the contact metal layer.

17. The method of claim 15, further comprising:

between the forming a cap layer and the forming a contact metal layer, forming a dielectric layer over the cap layer.

18. The method of claim 17, wherein:

the dielectric layer includes at least one selected from the group consisting of silicon nitride, aluminum oxide and lanthanum oxide.

19. The method of claim 15, wherein:

the contact hole is formed in the interlayer dielectric layer so as to expose the source/drain structures, while maintaining coverage of a top surface of a metal electrode of the one or more gate structures by the interlayer dielectric layer.