Switching converter with an adjustable transistor component

• US 9,742,277 B2
• Filed: 09/14/2015
• Issued: 08/22/2017
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Feldtkeller, Martin, Deboy, Gerald
• Primary Examiner(s): Torres-Rivera, Alex
• Application Number:
  US14/853,379
• Publication Number:
  US 20160006353A1
• Time in Patent Office: 708 Days
• Field of Search: 323266, 323268, 323272, 323282
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A switching converter includes a transistor arrangement having a plurality of n transistors, with n≧2, each including a gate terminal, and a load path between a source and a drain terminal, and at least m, with m≦n and m≧1 of the n transistors having a control terminal. The control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor. The load paths of the plurality of n transistors are connected in parallel to form a load path of the transistor arrangement. A drive circuit is configured to adjust the activation state of the m transistors.

Claims

1. A switching converter, comprising:

input terminals configured to apply an input voltage;

output terminals configured to provide an output voltage;

a rectifier-inductor arrangement coupled between the input terminals and the output terminals;

a control circuit configured to receive an output voltage signal that is dependent on the output voltage, to provide a drive signal, and to assume one of at least two different operation modes;

a transistor arrangement comprising a plurality of n transistors, with n>

2, each comprising a gate terminal, and a load path between a source and a drain terminal, and at least m, with m<

n and m>

1 of the n transistors comprising a control terminal, wherein the control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the m transistor, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement; and

a drive circuit configured to adjust the activation state of the m transistors independent of other ones of the plurality of n transistors to one of a first and second activation state, to determine a load condition of the transistor arrangement, and to select k, with k>

0, of the m transistors that are driven to assume the first activation state and m−

k of the m transistors that are driven to assume the second activation state dependent on the operation mode of the control circuit, wherein one of the operation modes is a burst mode, and one of the operation modes is a normal operation mode, wherein each of the n transistors has an active area, individual ones of the n transistors have identical sizes of their active area, and the drive circuit is configured to drive a first number of the k transistors to assume the first activation when the control circuit is in the normal operation mode, and to drive a second number of the k transistors to assume the first activation state when the control circuit is in the burst mode, wherein the second number is lower than the first number.

2. The switching converter of claim 1, wherein the first number equals the number n of transistors of the transistor arrangement.

3. The switching converter of claim 1, wherein the second number is between 0.1 times n and 0.6 times n.

4. The switching converter of claim 3, wherein in the normal operation mode, a sum of the sizes of the active areas of the k transistors in the first activation state equals an overall size of the active areas of the n transistors.

5. The switching converter of claim 1, wherein in the burst mode, the sum of the sizes of the active areas of the k transistors in the first activation state is between 0.1 times n and 0.6 times n.

6. The switching converter of claim 1, wherein the rectifier-inductor arrangement has one of a buck topology, a boost topology, a buck-boost topology, or a flyback topology.

7. A switching converter, comprising:

input terminals configured to apply an input voltage;

output terminals configured to provide an output voltage;

a rectifier-inductor arrangement coupled between the input terminals and the output terminals;

a control circuit configured to receive an output voltage signal that is dependent on the output voltage, to provide a drive signal, and to assume one of at least two different operation modes;

a transistor arrangement comprising a plurality of n transistors, with n>

2, each comprising a gate terminal, and a load path between a source and a drain terminal, and at least m, with m<

n and m>

1 of the n transistors comprising a control terminal, wherein the control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the m transistor, and wherein the load paths of the plurality of n transistors are connected in parallel forming a load path of the transistor arrangement; and

a drive circuit configured to adjust the activation state of the m transistors independent of other ones of the plurality of n transistors to one of a first and second activation state, to determine a load condition of the transistor arrangement, and to select k, with k>

0, of the m transistors that are driven to assume the first activation state and m−

k of the m transistors that are driven to assume the second activation state dependent on the operation mode of the control circuit,

wherein the drive signal generated by the control circuit is received by the gate terminals of the n transistors,

wherein the drive circuit is configured to adjust the activation state of each of the m transistors by generating the control signal,

wherein the k transistors are driven to assume the first activation state and the m−

k transistors are driven to assume the second activation state by driving the k transistors and the m−

k transistors such that the k transistors have an on-resistance different from an on-resistance of the m−

k transistors.

8. The switching converter of claim 7, wherein one of the operation modes is a burst mode, and one of the operation modes is a normal operation mode.

9. The switching converter of claim 8, wherein each of the n transistors has an active area, the individual transistors have identical sizes of their active area, and the drive circuit is configured to drive a first number of the k transistors to assume the first activation state when the control circuit is in the normal operation mode, and to drive a second number of the k transistors to assume the first activation state when the control circuit is in the burst mode, wherein the second number is lower than the first number.

10. The switching converter of claim 9, wherein the first number equals the number n of transistors of the transistor arrangement.

11. The switching converter of claim 9, wherein the second number is between 0.1 times n and 0.6 times n.

12. The switching converter of claim 8, wherein each of the n transistors has an active area, at least some of the n transistors have different sizes of their active areas, and the drive circuit is configured to select the k transistors that are in the first activation state such that a sum of the sizes of the active areas of the k transistors in the first activation state is lower when the control circuit is in the burst mode than in the normal operation mode.

13. The switching converter of claim 12, wherein in the normal operation mode, the sum of the sizes of the active areas of the k transistors in the first activation state equals an overall size of the active areas of the n transistors.

14. The switching converter of claim 12, wherein in the burst mode, the sum of the sizes of the active areas of the k transistors in the first activation state is between 0.1 times n and 0.6 times n.

15. The switching converter of claim 7, wherein the rectifier-inductor arrangement has one of a buck topology, a boost topology, a buck-boost topology, or a flyback topology.