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Network node physical/communication pins, state machines, interpreter and executor circuitry

  • US 9,742,847 B2
  • Filed: 08/30/2013
  • Issued: 08/22/2017
  • Est. Priority Date: 08/30/2013
  • Status: Active Grant
First Claim
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1. A programmable system node comprising:

  • (a) physical environment pins for at least one of a sensor input pin and a control output pin;

    (b) network node communication pins separate from the physical environment pins;

    (c) an embedded microcontroller unit, including;

    (i) memory circuitry for storing program code, data, and state variables;

    (ii) interpreter logic circuitry coupled to the communication pins and programmed to interpret commands and instructions received on the communication pins into machine language executable program code and internal control signals;

    (iii) state machines, each state machine includes program code corresponding to one sequence of instructions in a set of instructions, the state machines being coupled to the physical environment pins and the state variables of the memory circuitry, and each state machine being separately selectable; and

    (iv) executor logic circuitry coupled to the interpreter logic circuitry and to the state machines to select a state machine to carry out the interpreted commands and instructions from the interpreter logic circuitry, the executor logic circuitry initiating and continuing execution of the selected state machine, in which the executor logic circuitry receives a PUT command selecting the selected state machine for execution and setting a signal value at a pin associated with that particular state machine.

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