IC interposer with TAP controller and output boundary scan cell

• US 9,746,517 B2
• Filed: 08/03/2016
• Issued: 08/29/2017
• Est. Priority Date: 02/07/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US15/227,536
• Publication Number:
  US 20160341794A1
• Time in Patent Office: 391 Days
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Claims

1. An integrated circuit interposer comprising:

A. a substrate having a first side and an opposed second side;

B. first functional input pads formed on the first side of the substrate;

C. first functional output pads formed on the second side of the substrate and coupled to the first functional input pads;

D. second functional input pads formed on the second side of the substrate;

E. second functional output pads formed on the first side of the substrate and coupled to the second functional input pads;

F. a test data input pad, a test clock input pad, a test mode select input pad, and a test data output pad formed on the first side of the substrate;

G. a test access port controller, formed on the substrate, coupled to the test clock input pad and the test mode select input pad, and having a control output bus; and

H. boundary register circuitry formed on the substrate, the boundary register circuitry including output boundary scan cells, each output boundary scan cell including a functional input coupled to a second functional input pad, a functional output coupled to a second functional output pad, a test data input coupled to the test data input pad, a test data output coupled to the test data output pad, and a control input coupled to the control output bus of the test access port controller, each output boundary scan cell including;

i. a capture shift update cell that is coupled between the functional input and the functional output, the capture shift update cell also being coupled between the test data input and the test data output, and the capture shift update cell also being coupled to the control input, and

ii. multiplexer circuitry that is coupled between the functional input and output and is also coupled between the capture shift update cell and the second functional output pad.

2. The integrated circuit interposer of claim 1 including a base substrate carrying the integrated circuit interposer, the base substrate having pads connected to the pads on the first side of the integrated circuit interposer substrate.

3. The integrated circuit interposer of claim 1 including stacked integrated circuit die, carrying functional integrated circuits, coupled to the pads on the second side of the integrated circuit interposer substrate.