Methods for reprogramming data and apparatuses using the same

• US 9,747,206 B2
• Filed: 09/23/2015
• Issued: 08/29/2017
• Est. Priority Date: 03/04/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Hsu, Che-Wei
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US14/862,697
• Publication Number:
  US 20160259679A1
• Time in Patent Office: 706 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A method for reprogramming data, performed by a processing unit, is disclosed to include at least the following steps. After a page of data has failed to be programmed into a first block of a storage unit, it is determined whether the failed page is an upper page or a first lower page. When the failed page is an upper page, a host page number associated with a second lower page of a wordline including at least the failed page is obtained, a second block is selected, and an access interface is directed to reprogram data from the second lower page to the upper page into the second block.

Claims

1. A method for reprogramming data, performed by a processing unit, comprising:

after inspecting that a page of data has failed to be programmed into a first block of a storage unit, determining, by the processing unit, whether the failed page is an upper page or a first lower page of the first block;

determining, by the processing unit, whether the page of data has failed to be programmed into the first block of the storage unit;

when the failed page is the upper page of the first block, obtaining, by the processing unit, a host page number associated with a second lower page of a plurality of memory cells of the first block of a wordline, wherein the memory cells comprises the failed page;

when the failed page is the upper page of the first block, selecting, by the processing unit, a second block of the storage unit; and

when the failed page is the upper page of the first block, directing, by the processing unit, an access interface to reprogram data from the second lower page to the upper page of the first block into the second block of the storage unit, wherein at least one intermediate page is present between the second lower page and the upper page of the first block, and the second lower page, the intermediate page and the upper page are associated with consecutive host page numbers,

wherein the step for determining whether the page of data has failed to be programmed into the first block of the storage unit further comprises

inspecting, by the processing unit, a register through the access interface to determine whether the page of data has failed to be programmed into the first block of the storage unit, wherein the register is set by control circuits to notify the processing unit an execution outcome associated with a programming of the page of data.

2. The method of claim 1, wherein each memory cell stores information of a LSB (Least Significant Bit) and a MSB (Most Significant Bit), the LSBs of the memory cells collectively form the second lower page of the first block and the MSBs of the memory cells collectively form the upper page of the first block.

3. The method of claim 1, further comprising:

when the failed page is the upper page of the first block, reading, by the processing unit, data associated with the consecutive host page numbers from a DRAM (Dynamic Random Access Memory) and storing the read data in a data buffer; and

when the failed page is the upper page of the first block, directing the access interface to program the data of the data buffer into the second block.

4. The method of claim 1, further comprising:

when the failed page is the first lower page of the first block, selecting, by the processing unit, the second block; and

when the failed page is the first lower page of the first block, directing, by the processing unit, the access interface to program data of the first lower page into the second block.

5. The method of claim 1, further comprising:

filling, by the processing unit, unused pages of the first block with dummy values.

6. The method of claim 1, further comprising:

setting, by the processing unit, a physical storage location associated with the host page number, which is stored in a storage mapping table, to point to the second block.

7. An apparatus for reprogramming data, comprising:

an access interface, coupled to a storage unit; and

a processing unit, coupled to the access interface, the processing unit,

after inspecting that a page of data has failed to be programmed into a first block of a storage unit, determining whether the failed page is an upper page or a first lower page of the first block;

determining whether the page of data has failed to be programmed into the first block of the storage unit;

inspecting a register setting through the access interface to determine whether the page of data has failed to be programmed into the first block of the storage unit;

when the failed page is the upper page of the first block, obtaining a host page number associated with a second lower page of a plurality of memory cells of the first block of a wordline, selecting a second block of the storage unit and directing an access interface to reprogram data from the second lower page to the upper page of the first block into the second block of the storage unit,

wherein the memory cells comprises the failed page, at least one intermediate page is present between the second lower page and the upper page of the first block, and the second lower page, the intermediate page and the upper page are associated with consecutive host page numbers,

wherein the register is set by control circuits to notify the processing unit an execution outcome associated with a programming of the page of data.

8. The apparatus of claim 7, wherein each memory cell stores information of a LSB (Least Significant Bit) and a MSB (Most Significant Bit), the LSBs of the memory cells collectively form the second lower page of the first block and the MSBs of the memory cells collectively form the upper page of the first block.

9. The apparatus of claim 7, wherein when the failed page is the upper page of the first block, the processing unit reads data associated with the consecutive host page numbers from a DRAM (Dynamic Random Access Memory), stores the read data in a data buffer and directs the access interface to program the data of the data buffer into the second block.

10. The apparatus of claim 7, wherein when the failed page is the first lower page of the first block, the processing unit selects the second block and directs the access interface to program data of the first lower page into the second block.

11. The apparatus of claim 7, wherein the processing unit further fills unused pages of the first block with dummy values.

12. The apparatus of claim 7, wherein the processing unit further sets a physical storage location associated with the host page number, which is stored in a storage mapping table, to point to the second block.