Caching systems and methods for execution within an NVDRAM environment
First Claim
1. A system, comprising:
- a host processor;
a host memory communicatively coupled to the host processor and sectioned into pages;
a host bus adapter (HBA) communicatively coupled to the host processor and comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations andan HBA driver operable on the host processor,wherein the DRAM is sectioned into pages mapped to pages of the host memory and the SSD is sectioned into pages mapped to pages of the DRAM,wherein the SSD is further sectioned into regions comprising one or more pages of the SSD, andwherein the HBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by the host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of a region of the page of the other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.
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Accused Products
Abstract
Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. AnHBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.
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Citations
20 Claims
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1. A system, comprising:
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a host processor; a host memory communicatively coupled to the host processor and sectioned into pages; a host bus adapter (HBA) communicatively coupled to the host processor and comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations and an HBA driver operable on the host processor, wherein the DRAM is sectioned into pages mapped to pages of the host memory and the SSD is sectioned into pages mapped to pages of the DRAM, wherein the SSD is further sectioned into regions comprising one or more pages of the SSD, and wherein the HBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by the host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of a region of the page of the other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method operable in a host system comprising a host processor, a host memory, a host bus adapter (HBA), and an HBA driver, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations, the method comprising:
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sectioning the host memory into pages; sectioning the DRAM into pages; sectioning the SSD into pages and regions, with each region of the SSD comprising one or more pages of the SSD; mapping the host memory pages to the DRAM pages; mapping the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM; loading a page of data from the SSD into a page of the DRAM when directed by the host processor; determining that the page of the DRAM is occupied with other data;
determining a priority of the region of the page of other data occupying the page of the DRAM; andflushing the other data from the DRAM to the SSD based on the determined priority. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A non-transitory computer readable medium comprising instructions that, when directed by a processor in a host system comprising a host memory, a host bus adapter (HBA), and an HBA driver, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations, direct the processor to:
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section the host memory into pages; section the DRAM into pages; section the SSD into pages and regions, with each region of the SSD comprising one or more pages of the SSD; map the host memory pages to the DRAM pages; map the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM; load a page of data from the SSD into a page of the DRAM when directed by the host processor; determine that the page of the DRAM is occupied with other data; determine a priority of the region of the page of other data occupying the page of the DRAM; and flush the other data from the DRAM to the SSD based on the determined priority. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification