Data transmission system including encoder and a clock recovery system for display device, data transmission method for display device and display device

• US 9,747,830 B2
• Filed: 06/01/2015
• Issued: 08/29/2017
• Est. Priority Date: 03/29/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Sugiyama, Akio, Nose, Takashi, Hori, Yoshihiko, Furihata, Hirobumi
• Primary Examiner(s): Lin, Hang
• Application Number:
  US14/726,904
• Publication Number:
  US 20150262522A1
• Time in Patent Office: 820 Days
• Field of Search: 341 50-107, 345204-215
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 2370/00 Aspects of data communication
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level

Abstract

A display device includes an encoder having at least one translation table, and encoding m (m is a natural number) bits of a data to n (n is a natural number and n>m) bits of a data on a basis of the at least one translation table; a clock recovery circuit configured to recover a clock from the data encoded by the encoder; a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit; an output driver configured to output a voltage in accordance with the data decoded by the decoder; and a display element having a pixel applied with the voltage.

Claims

1. A display device comprising:

an encoder having at least one translation table, and encoding m (m is a natural number) bits of a data to n (n is a natural number and n>

m) bits of a data on a basis of the at least one translation table;

a clock recovery circuit configured to recover a clock from the data encoded by the encoder;

a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit;

an output driver configured to output a voltage in accordance with the data decoded by the decoder; and

a display element having a pixel applied with the voltage,

wherein, in the at least one translation table, a larger an amplitude of the voltage of a bit pattern in 2^m pieces of bit patterns of the m bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern in the 2^m pieces of bit patterns in 2ⁿ piece of bit patterns of the n bits of the data,

wherein the at least one translation table is only one translation table for a normally first color mode or for a normally second color mode.

2. The display device according to claim 1, further comprising:

a data generating circuit configured to convert the data inputted to the encoder in accordance with a first display mode signal.

3. The display device according to claim 2, further comprising:

a data converter configured to convert the data outputted from the decoder in accordance with a second display mode signal.

4. The display device according to claim 1, further comprising:

a data converter configured to convert the data outputted from the decoder in accordance with a display mode signal.

5. The display device according to claim 4, further comprising:

a data generating circuit configured to convert the data inputted to the encoder in accordance with another display mode signal.

6. The display device according to claim 1, wherein the encoder includes a first translation table for the normally first color mode as the at least one translation table, and in the first translation table, a larger a data value of the bit pattern in the 2^m pieces of bit patterns of the m bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern in the 2^m pieces of bit patterns in the 2ⁿ pieces of bit patterns of the n bits of the data.

7. The display device according to claim 1, wherein the encoder includes a second translation table for the normally second color mode as the at least one translation table, and in the second translation table, a smaller a data value of the bit pattern in the 2^m pieces of bit patterns of the m bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern hi the 2^m pieces of bit patterns in the 2ⁿ pieces of bit patterns of the n bits of the data.

8. The display device according to claim 3, further comprising:

a first register configured to store the first display mode signal; and

a second register configured to store the second display mode signal.

9. The display device according to claim 3;

wherein the first and the second display mode signals comprise signals indicating the normally first color mode or the normally second color mode.

10. The display device according to claim 1, further comprising:

a parallel-to-serial converter configured to subject the encoded data outputted from the encoder to a parallel-to-serial conversion; and

a serial-to-parallel converter configured to subject the data outputted from the parallel-to-serial converter to a serial-to-parallel conversion.

11. The display device according to claim 1, wherein the encoder includes a first translation table for the normally first color mode as the at least one translation table, a larger a data value of the bit pattern in the 2^m pieces of bit patterns of the m bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern in the 2^m pieces of bit patterns in the 2ⁿ pieces of bit patterns of the n bits of the data.

12. The display device according to claim 1, wherein the encoder includes a second translation table for the normally second color mode as the at least one translation table, and in the second translation table, a smaller a data value of the bit pattern in the 2^m pieces of bit patterns of the m bits of the data, a larger a data change index of the bit pattern which is assigned to the bit pattern in the 2^m pieces of bit patterns in the 2ⁿ pieces of bit patterns of the n bits of the data.

13. The display device according to claim 5, further comprising:

a first register configured to store the display mode signal; and

a second register configured to store the another display mode signal.

14. The display device according to claim 5, wherein the display mode signal and the another display mode signal comprise signals indicating the normally first color mode or the normally second color mode.

15. The display device according to claim 3, further comprising:

a parallel-to-serial converter configured to subject the encoded data outputted from the encoder to a parallel-to-serial conversion; and

a serial-to-parallel converter configured to subject the data outputted from the parallel-to-serial converter to a serial-to-parallel conversion.

16. The display device according to claim 2, wherein the data generating circuit converts the data by either regularly converting or inversely converting the data.

17. The display device according to claim 1, wherein the display element includes a plurality of pixels for receiving the voltage.

18. The display device according to claim 1, wherein said voltage comprises a gray scale voltage.

19. The display device according to claim 1, wherein the normally first color mode comprises a black mode, and the normally second color mode comprises a white mode.

20. A display device comprising:

a translation table configured to encode m (m is a natural number) bits of a data to n (n is a natural number and n>

m) bits of a data;

a clock recovery circuit configured to recover a clock from the data encoded with the translation table;

a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit;

an output driver configured to output a voltage in accordance with the data decoded by the decoder; and

a display element having a pixel applied with the voltage,

wherein, in the translation table, a value of an amplitude of the voltage of a bit pattern in 2^m pieces of bit patterns of the m bits of the data, is proportional to a value of a data change index of the bit pattern which is assigned to the bit pattern in the 2^m pieces of bit patterns in 2ⁿ piece of bit patterns of the n bits of the data,

wherein the translation table is only one translation table for a normally first color mode or for a normally second color mode.