Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating

• US 9,747,983 B2
• Filed: 02/17/2017
• Issued: 08/29/2017
• Est. Priority Date: 02/07/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/436,641
• Publication Number:
  US 20170169887A1
• Time in Patent Office: 193 Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Claims

1. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:

a substrate;

a floating body region configured to store volatile memory;

a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and

a select gate positioned adjacent said substrate and said floating gate.

2. The semiconductor memory array of claim 1, wherein said floating body is exposed at a surface of said substrate, each said semiconductor memory cell further comprising:

first and second regions each exposed at said surface at locations other than where said floating body region is exposed;

wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

3. The semiconductor memory array of claim 2, wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.

4. The semiconductor memory array of claim 2, further comprising a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region.

5. The semiconductor memory array of claim 4, wherein said floating body is bounded by said surface, said first and second regions and said buried layer.

6. The semiconductor memory array of claim 1, further comprising insulating layers bounding side surfaces of said substrate.

7. The semiconductor memory array of claim 2, further comprising a buried insulator layer buried in a bottom portion of said substrate.

8. The semiconductor memory array of claim 7, wherein said floating body is bounded by said surface, said first and second regions and said buried insulator layer.

9. A semiconductor memory cell comprising:

a substrate;

a floating body region configured to store volatile memory;

a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region;

a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and

a select gate positioned adjacent said substrate and said floating gate;

wherein applying a bias to said buried layer results in at least two stable floating body region charge levels.

10. The semiconductor memory cell of claim 9, wherein said floating body is exposed at a surface of said substrate, said cell further comprising:

first and second regions each exposed at said surface at locations other than where said floating body region is exposed;

wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

11. The semiconductor memory cell of claim 10, wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.

12. The semiconductor memory cell of claim 10, wherein said floating body is bounded by said surface, said first and second regions and said buried layer.

13. The semiconductor memory cell of claim 9, further comprising insulating layers bounding side surfaces of said substrate.

14. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising:

a substrate;

a floating body region configured to store volatile memory;

a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region;

a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; and

a select gate positioned adjacent said substrate and said floating gate;

wherein said buried layer region is commonly connected to at least two of said memory cells, configured to inject charge into or extract charge out of said floating body region of each of said memory cells connected thereto, to maintain said state of the memory cells in parallel.

15. The semiconductor memory array of claim 14, wherein said floating body is exposed at a surface of said substrate, said cell further comprising:

first and second regions each exposed at said surface at locations other than where said floating body region is exposed;

wherein said first and second regions are asymmetric, wherein a first area defines an area over which said first region is exposed at said surface and a second area defines an area over which said second region is exposed at said surface, and wherein said first area is unequal to said second area.

16. The semiconductor memory array of claim 15, wherein one of said first and second regions at the surface has a higher coupling to said floating gate relative to coupling of the other of said first and second regions to said floating gate.

17. The semiconductor memory array of claim 15, wherein said floating body is bounded by said surface, said first and second regions and said buried layer.

18. The semiconductor memory array of claim 14, further comprising insulating layers bounding side surfaces of said substrate.