Non-volatile memory with customized control of injection type of disturb during read operations

• US 9,747,992 B1
• Filed: 06/03/2016
• Issued: 08/29/2017
• Est. Priority Date: 06/03/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Dong, Yingda
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/172,671
• Time in Patent Office: 452 Days
• Field of Search: 36518503, 36518517, 36518533, 36518523, 36518524, 36518909
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.

Claims

1. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells; and

one or more control circuits in communication with the memory cells, the one or more control circuits are configured to apply one or more signals to perform boosting of a channel region associated with an unselected memory cell, the one or more control circuits are configured to temporarily mitigate the boosting of the channel region while applying the one or more signals to perform boosting for a duration of time based on position of a selected memory cell, subsequent to the duration of time the boosting continues while applying the one or more signals to perform boosting, the one or more control circuits are configured to apply a compare signal to the selected memory cell and sense the selected memory cell in response to the compare signal after the mitigating the boosting.

2. The non-volatile storage apparatus of claim 1, wherein:

the duration of time is a first duration if the selected memory cell is an edge memory cell; and

the duration of time is a second duration if the selected memory cell is a middle memory cell, the first duration is longer than the second duration.

3. The non-volatile storage apparatus of claim 1, wherein:

the selected memory cell and the unselected memory cell are part of a group of connected memory cells, the group of connected memory cells has one or more end regions and a middle region;

the duration of time is a first duration if the selected memory cell is in one of the end regions; and

the duration of time is a second duration if the selected memory cell is in the middle region the first duration is longer than the second duration.

4. The non-volatile storage apparatus of claim 1, further comprising:

a set of word lines including a selected word line and unselected word lines, the selected word line is connected to the selected memory cell and the unselected memory cell;

the duration of time is a first duration if the selected word line is an edge word line; and

the duration of time is a second duration if the selected word line is a middle word line, the first duration is longer than the second duration.

5. The non-volatile storage apparatus of claim 1, further comprising:

a set of word lines including a selected word line and unselected word lines, the selected word line is connected to the selected memory cell and the unselected memory cell, the set of word lines includes end regions and a middle region;

the duration of time is a first duration if the selected memory cell is the end regions; and

the duration of time is a second duration if the selected memory cell is in the middle region the first duration is longer than the second duration.

6. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are organized into groups of memory cells that include select gates; and

the temporarily mitigating the boosting of the channel region includes applying a voltage spike to a select gate for unselected groups of memory cells.

7. The non-volatile storage apparatus of claim 1, wherein:

the non-volatile memory cells are arranged in groups of connected non-volatile memory cells;

the selected memory cell is in a selected group of connected non-volatile memory cells;

the selected group of connected non-volatile memory cells has a first end and a second end;

the one or more control circuits are configured to program memory cells in the selected group in an order from the first end to the second end; and

the one or more control circuits are configured to temporarily mitigate the boosting of the channel region while applying the one or more signals to perform boosting for a duration of time based on position of the selected memory cell with respect to the first end of the selected group.

8. The non-volatile storage apparatus of claim 1, further comprising:

word lines, the non-volatile memory cells are arranged in groups of connected non-volatile memory cells, the word lines are connected to the in groups of connected non-volatile memory cells, the one or more control circuits are configured to temporarily mitigate the boosting of the channel region while applying the one or more signals to perform boosting for a duration of time based on word line position of the selected memory cell.

9. The non-volatile storage apparatus of claim 1, wherein:

the non-volatile memory cells are arranged in vertical NAND strings that form a monolithic three dimensional memory structure, the vertical NAND strings each include a charge trapping layer; and

the one or more control circuits are configured to temporarily mitigate the boosting of the channel region while applying the one or more signals to perform boosting for a duration of time based on position of the selected memory cell in a NAND string.

10. The non-volatile storage apparatus of claim 1, further comprising:

word lines, the non-volatile memory cells are arranged in NAND strings that include one or more select gates, the word lines are connected to the non-volatile memory cells of the NAND strings; and

select lines connected to the one or more select gates;

wherein the one or more control circuits are configured to apply a voltage to one or more select lines for selected NAND strings to turn on one or more select gates for selected NAND strings, apply a voltage to one or more select lines for unselected NAND strings to turn off one or more select gates for selected NAND strings, apply and increase a boosting voltage to unselected word lines to boost channels of unselected NAND strings such that the unselected word lines are connected to the selected NAND strings and the unselected NAND strings, apply a compare voltage to a selected word line connected to the selected NAND string and the unselected NAND strings, sense a threshold voltage of selected memory cells in the selected NAND strings in response to the compare voltage, and while increasing the boosting voltage, temporarily change the voltage applied to the select lines for unselected NAND strings to temporarily turn on the select gates for unselected NAND strings in order to prevent boosting of the channels of the unselected NAND strings for a duration of time based on position of the selected word line.

11. The non-volatile storage apparatus of claim 1, wherein:

the unselected memory cell is part of a NAND string; and

the channel region associated with the unselected memory cell is a channel region for the NAND string.

12. The non-volatile storage apparatus of claim 1, wherein:

the plurality of non-volatile memory cells are arranged in a monolithic three dimensional memory structure.

13. A method of reading non-volatile storage, comprising:

applying a signal to one or more select gates for selected groups of memory cells to turn on the one or more select gates for selected groups of memory cells;

applying a signal to one or more select gates for unselected selected groups of memory cells to turn off the one or more select gates for the unselected groups of memory cells;

applying and increasing a signal to unselected control lines to boost channels of the unselected groups of memory cells, the unselected control lines are connected to the selected groups of memory cells and the unselected groups of memory cells;

applying a signal to a selected control line connected to the selected groups of memory cells and the unselected groups of memory cells;

sensing selected memory cells in the selected groups of memory cells in response to the signal applied to the selected control line; and

while increasing the signal to unselected control lines to boost channels, temporarily changing the signal applied to the select gates for unselected groups of memory cells to temporarily turn on the select gates for the unselected groups of memory cells in order to prevent an increase in the boosting of the channels of the unselected groups of memory cells for a duration of time based on position of the selected control line with respect to a group of control lines that comprise the unselected control lines and the selected control line and subsequently turn off the select gates for the unselected groups of memory cells in order to continue increasing the boosting of the channels of the unselected groups of memory cells.

14. The method of claim 13, wherein:

the unselected control lines and the selected control line are word lines;

the duration of time is a first duration if the selected control line is an edge word line; and

the duration of time is a second duration if the selected control line is a middle word line, the first duration is longer than the second duration.

15. The method of claim 13, wherein:

the group of control lines includes a first zone of control lines at a first end of the group of control lines, a second zone of control lines at a second end of the group of control lines and a third zone between the first zone and the second zone;

the duration of time is a first duration if the selected control line is in the first zone or the second zone; and

the duration of time is a second duration if the selected control line is in the third zone, the first duration is longer than the second duration.

16. The method of claim 13, wherein:

the temporarily changing the signal applied to the select gates for unselected groups of memory cells includes applying a voltage spike to the select gates for unselected groups of memory cells.

17. The method of claim 13, wherein:

the temporarily changing the signal applied to the select gates for unselected groups of memory cells temporarily interrupts boosting that has already started.

18. The method of claim 13, wherein:

the control lines are word lines; and

the non-volatile memory cells are arranged in vertical NAND strings of a monolithic three dimensional memory structure.

19. A non-volatile storage apparatus, comprising:

a plurality of non-volatile memory cells;

a plurality of select gates;

a plurality of word lines connected to the memory cells;

a plurality of select lines connected to the select gates; and

means for sensing the non-volatile memory cells, the means for sensing is connected to the word lines and the select lines, the means for sensing includes means for reducing hot electron injection disturb based on selected word line position.

20. The non-volatile storage apparatus of claim 19, wherein:

the non-volatile memory cells and the select gates are arranged in vertical NAND strings;

the means for reducing hot electron injection disturb based on selected word line position comprises one or more control circuits in communication with the select lines and word lines; and

the one or more control circuits are configured to sense data in memory cells by applying a voltage to one or more select lines for selected NAND strings to turn on one or more select gates for selected NAND strings, applying a voltage to one or more select lines for unselected NAND strings to turn off one or more select gates for unselected NAND strings, applying and increasing a boosting voltage to unselected word lines to boost channels of unselected NAND strings such that the unselected word lines are connected to the selected NAND strings and the unselected NAND strings, applying a compare voltage to a selected word line connected to the selected NAND strings and the unselected NAND strings, sensing a threshold voltage of selected memory cells in the selected NAND strings in response to the compare voltage, and while increasing the boosting voltage, temporarily changing the voltage applied to the select lines for unselected NAND strings to temporarily turn on the select gates for unselected NAND strings in order to interrupt boosting of the channels of the unselected NAND strings for a duration of time based on position of the selected word line and subsequently turn off the select gates for unselected NAND strings to allow boosting to continue.