Memory systems

• US 9,747,993 B2
• Filed: 08/13/2013
• Issued: 08/29/2017
• Est. Priority Date: 08/13/2013
• Status: Expired due to Fees

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Lee, Hyoung-Gon
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/908,340
• Publication Number:
  US 20160211033A1
• Time in Patent Office: 1,477 Days
• Field of Search: 36518502, 36518524
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Technologies are generally described for a memory system that may be a solid-state drive (SDD). The memory system may include memory blocks, where each memory block may have multiple memory pages, and each memory page may have multiple memory cells. The memory cells may have multiple programmed states. In various examples, a method to control the memory system may include determining one or more memory pages to be analyzed, identifying read threshold voltages of each memory cell associated with the memory pages to be analyzed, performing statistical analysis on the identified read threshold voltages, and determining a distribution of the read threshold voltages based at least in part on the statistical analysis.

Claims

1. A method to control a memory system that includes memory blocks, wherein each memory block has memory pages, and each memory page has memory cells, the method to control the memory system comprising:

determining one or more memory pages to be analyzed;

identifying read threshold voltages of each memory cell associated with the determined one or more memory pages to be analyzed;

calculating a read disturb count for a respective one of the determined one or more memory pages, wherein the identified read threshold voltages are associated with the read disturb count;

performing statistical analysis on the identified read threshold voltages associated with the read disturb count;

determining a distribution of the identified read threshold voltages associated with the read disturb count based, at least in part, on the statistical analysis; and

decoding data written on at least one memory page of the memory system based, at least in part, on the determined distribution of the identified read threshold voltages.

2. The method of claim 1, wherein the determining the one or more memory pages to be analyzed is performed at a specific time interval, after each memory page is invalidated, when the memory block that includes the memory pages is to be erased, or after a specific number of accesses.

3. The method of claim 1, wherein the determining the distribution of the identified read threshold voltages comprises determining a distribution model and at least one associated parameter of the distribution model.

4. The method of claim 1, wherein the calculating the read disturb count for the respective one of the determined one or more memory pages comprises calculating a sum of read counts of other memory pages associated with a memory block that includes the respective one of the determined one or more memory pages.

5. A method to control a memory system that includes memory blocks, wherein each memory block has memory pages, and each memory page has memory cells, the method to control the memory system comprising:

determining one or more memory pages to be analyzed;

identifying read threshold voltages of each memory cell associated with the determined one or more memory pages to be analyzed;

calculating a read disturb count for a respective one of the determined one or more memory pages, wherein the identified read threshold voltages are associated with the read disturb count;

performing statistical analysis on the identified read threshold voltages associated with the read disturb count;

determining a distribution of the identified read threshold voltages associated with the read disturb count based, at least in part, on the statistical analysis,

wherein the calculating the read disturb count for the respective one of the determined one or more memory pages comprises calculating a sum of read counts of other memory pages associated with a memory block that includes the respective one of the determined one or more memory pages;

reading data that is written on one of the memory pages of the memory system;

calculating a target read disturb count for the memory page on which the data is written, as a sum of read counts of other memory pages associated with a memory block that includes the memory page on which the data is written;

determining a target distribution of the identified read threshold voltages that are associated with the target read disturb count; and

decoding the data based, at least in part, on the determined target distribution.

6. A method to control a memory system that includes memory blocks, wherein each memory block has memory pages, and each memory page has memory cells, the method to control the memory system comprising:

determining one or more memory pages to be analyzed;

identifying read threshold voltages of each memory cell associated with the determined one or more memory pages to be analyzed;

calculating a read disturb count for a respective one of the determined one or more memory pages, wherein the identified read threshold voltages are associated with the read disturb count;

performing statistical analysis on the identified read threshold voltages associated with the read disturb count; and

determining a distribution of the identified read threshold voltages associated with the read disturb count based, at least in part, on the statistical analysis,

wherein the determining the distribution of the identified read threshold voltages comprises varying the distribution of the identified read threshold voltages depending on the read disturb count, and

wherein the calculating the read disturb count for the respective one of the determined one or more memory pages comprises calculating a sum of read counts of other memory pages associated with a memory block that includes the respective one of the memory pages.

7. The method of claim 6, wherein the varying the distribution of the identified read threshold voltages comprises modifying the distribution of the identified read threshold voltages to be asymmetric as the read disturb count increases.

8. A memory system, comprising:

a plurality of memory blocks, wherein each memory block includes memory pages, and each memory page includes memory cells; and

a memory controller coupled to the plurality of memory blocks, wherein the memory controller is configured to;

identify one or more memory blocks to be erased;

identify read threshold voltages of each memory cell of each memory page of each identified memory block;

calculate a read disturb count for each memory page of each identified memory block, wherein the identified read threshold voltages are associated with the read disturb count;

perform statistical analysis on the identified read threshold voltages associated with the read disturb count;

determine a distribution of the identified read threshold voltages associated with the read disturb count based at least in part on the statistical analysis; and

decode data stored in the plurality of memory blocks based at least in part on the determined distribution of the identified read threshold voltages.

9. The memory system of claim 8, wherein the memory controller is configured to:

calculate the read disturb count for each memory page of each identified memory block as a sum of read counts of other memory pages of a memory block that includes each memory page.

10. The memory system of claim 8, wherein the memory system includes a solid-state drive (SSD).

11. The memory system of claim 9, wherein the memory controller is configured to:

read data that is written on one of the memory pages of the memory system;

calculate a target read disturb count for the memory page on which the data is written, as a sum of read counts of other memory pages associated with a memory block that includes the memory page on which the data is written;

determine a target distribution of the identified read threshold voltages that is associated with the target read disturb count; and

decode the data based, at least in part, on the determined target distribution.

12. The memory system of claim 9, wherein to determine the distribution of the identified read threshold voltages, the memory controller is configured to vary the distribution of the identified read threshold voltages depending on the read disturb count.

13. The memory system of claim 12, wherein to vary the distribution of the identified read threshold voltages, the memory controller is configured to modify the distribution of the identified read threshold voltages to be asymmetric as the read disturb count increases.