Method for fabricating semiconductor package
First Claim
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1. A method for fabricating a semiconductor package, comprising:
- forming at least one conductive via in a wafer, wherein the wafer comprises a silicon substrate, a top silicon layer, and a buried dielectric layer disposed between the silicon substrate and the top silicon layer, wherein the top silicon layer is in contact with the buried dielectric layer, and the at least one conductive via extends through the top silicon layer and the buried dielectric layer;
grinding a surface of the silicon substrate of the wafer opposite the buried dielectric layer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than a thickness of the ring portion; and
etching the inner portion to expose an end of the at least one conductive via.
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Abstract
A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.
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Citations
19 Claims
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1. A method for fabricating a semiconductor package, comprising:
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forming at least one conductive via in a wafer, wherein the wafer comprises a silicon substrate, a top silicon layer, and a buried dielectric layer disposed between the silicon substrate and the top silicon layer, wherein the top silicon layer is in contact with the buried dielectric layer, and the at least one conductive via extends through the top silicon layer and the buried dielectric layer; grinding a surface of the silicon substrate of the wafer opposite the buried dielectric layer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than a thickness of the ring portion; and etching the inner portion to expose an end of the at least one conductive via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification