Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance

• US 9,748,114 B2
• Filed: 02/26/2015
• Issued: 08/29/2017
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Iyer, Subramanian S., Kerber, Pranita, Khakifirooz, Ali
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US14/632,531
• Publication Number:
  US 20150179548A1
• Time in Patent Office: 915 Days
• Field of Search: 438667, 438675, 438514
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance.

Claims

1. A method comprising:

forming an n+ epitaxy layer on top of a p-doped semiconductor substrate;

forming a device layer on the epitaxy layer;

forming a trench having a dielectric liner and conductive core within the trench to form a through-silicon via conductor, such that the trench extends through the epitaxy layer and the p-doped semiconductor substrate; and

implanting a p-doped region within the p-doped semiconductor substrate in contact with the p-doped semiconductor substrate and n+ epitaxy layer, beneath the epitaxy layer and adjacent to the through-silicon via conductor, wherein the p-doped region is formed of a higher dopant concentration that of the p-doped semiconductor substrate.

2. The method of claim 1, wherein, the p-doped region is formed by performing angled implantation p-dopants.

3. The method of claim 2, wherein the p dopants comprise boron (B) or Iridium (In).

4. The method of claim 2, wherein the angled implantation is performed after the trench is formed and prior to forming the dielectric liner within the trench.

5. The method of claim 2, wherein the angled implantation is performed after the trench and the dielectric liner are formed, such that the implantation is performed through the dielectric liner.

6. The method of claim 2, wherein the angled implantation is performed from at least four different angles.

7. The method of claim 2, further comprising:

forming a photoresist layer on the device layer; and

performing the angled implantation after forming the photoresist layer on the device layer.

8. The method of claim 2, further comprising annealing the p-doped region in order to activate the p-doped region after performing the angled implantation.

9. The method of claim 8, wherein the annealing comprises low temperature annealing at a temperature selected such that n dopants in the epitaxy layer are not diffused into the p-doped region.

10. The method of claim 8, wherein the annealing comprises laser annealing.