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Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance

  • US 9,748,114 B2
  • Filed: 02/26/2015
  • Issued: 08/29/2017
  • Est. Priority Date: 09/30/2010
  • Status: Active Grant
First Claim
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1. A method comprising:

  • forming an n+ epitaxy layer on top of a p-doped semiconductor substrate;

    forming a device layer on the epitaxy layer;

    forming a trench having a dielectric liner and conductive core within the trench to form a through-silicon via conductor, such that the trench extends through the epitaxy layer and the p-doped semiconductor substrate; and

    implanting a p-doped region within the p-doped semiconductor substrate in contact with the p-doped semiconductor substrate and n+ epitaxy layer, beneath the epitaxy layer and adjacent to the through-silicon via conductor, wherein the p-doped region is formed of a higher dopant concentration that of the p-doped semiconductor substrate.

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