Single spacer for complementary metal oxide semiconductor process flow

• US 9,748,146 B1
• Filed: 08/18/2016
• Issued: 08/29/2017
• Est. Priority Date: 02/04/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Dechene, Jessica, Lie, Fee Li, Miller, Eric R., Shearer, Jeffrey C., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US15/240,578
• Publication Number:
  US 20170229350A1
• Time in Patent Office: 376 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.

Claims

1. A method of forming a fin structure comprising:

forming a high-k dielectric fin liner on at least one of a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region;

forming a low-k dielectric spacer on a channel region of said at least one of the first and second plurality of fin structures;

forming a first epitaxial semiconductor material on one for said first and second plurality of fin structures from which the high-k dielectric fin liner is removed, wherein a remaining portion of the high-k dielectric fin liner remains on a second of said first and second plurality of fin structures;

oxidizing the first epitaxial semiconductor material;

removing a remaining portion of the high-k dielectric fin liner; and

forming a second epitaxial semiconductor material on said second of said first and second plurality of fin structures.

2. The method of claim 1, wherein said forming the high-k dielectric fin liner on at least one of the first plurality of fin structures in the first device region and a second plurality of fin structures in the second device region comprises:

forming a material layer of high-k dielectric on the first and second plurality of fin structures;

forming a block mask over material layer of the high-k dielectric that is present over the second plurality of fin structures;

removing an exposed portion of the material layer of the high-k dielectric that is present over the first plurality of fin structures, wherein a remaining portion of the material layer of the high-k dielectric provides the high-k dielectric fin liner that is present on the second plurality of fin structures; and

removing the block mask.

3. The method of claim 2, wherein forming the low-k dielectric spacer comprises:

forming a gate structure;

depositing a low-dielectric layer on the gate structure and over the first and second plurality of fin structures; and

etching the low-dielectric layer to form the low-k dielectric spacer.

4. The method of claim 3, wherein the first epitaxial semiconductor material comprises germanium.

5. The method of claim 4, wherein said oxidizing the first epitaxial semiconductor material forms an oxide including said germanium that obstructs said second epitaxial semiconductor material from being formed on the first plurality of fin structures in the first device region.

6. The method of claim 5, wherein the first epitaxial semiconductor material is comprised of a p-type conductivity dopant, and the second epitaxial semiconductor material is comprised of an n-type conductivity dopant.

7. The method of claim 1, wherein said forming the high-k dielectric fin liner comprises depositing the high-k dielectric fin liner on said first plurality of fin structures and said second plurality of fin structures.

8. The method of claim 7, wherein the first epitaxial semiconductor material comprises germanium.

9. The method of claim 8, wherein said oxidizing the first epitaxial semiconductor material forms an oxide including said germanium that obstructs said second epitaxial semiconductor material from being formed on the first plurality of fin structures in the first device region.

10. The method of claim 9, wherein the first epitaxial semiconductor material is comprised of a p-type conductivity dopant.

11. The method of claim 10, wherein the second epitaxial semiconductor material is comprised of an n-type conductivity dopant.

12. The method of claim 7, wherein said forming the low-k dielectric spacer on the channel region of the at least one of the first and second plurality of fin structures comprises:

forming a gate structure on the first and second plurality of fin structures, wherein the gate structure is deposited atop the high-k dielectric fin liner;

forming said low-k dielectric spacer;

forming a block mask over the second plurality of fin structures in the second device region;

removing the high-k dielectric fin liner from the first device region, wherein the high-k dielectric fin liner remains in the second device region; and

removing the block mask.

13. The method of claim 12, wherein forming the low-k dielectric spacer comprises:

depositing a low-k dielectric layer on the gate structure and over the first and second plurality of fin structures; and

etching the low-k dielectric layer to form the low-k dielectric gate sidewall structure, wherein one of said low-k dielectric gate sidewall structure is present on the high-k dielectric fin liner.

14. The method of claim 13, wherein the first epitaxial semiconductor material comprises germanium.

15. The method of claim 14, wherein said oxidizing the first epitaxial semiconductor material forms an oxide including said germanium that obstructs said second epitaxial semiconductor material from being formed on the first plurality of fin structures in the first device region.

16. A method of forming a fin structure comprising:

forming a dielectric fin liner comprising hafnium and oxygen on at least one of a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region;

forming a SiOCN dielectric spacer on the channel region of said at least one of the first and second plurality of fin structures;

forming a first epitaxial semiconductor material on one for said first and second plurality of fin structures from which the dielectric fin liner is removed, wherein a remaining portion of the dielectric fin liner remains on a second of said first and second plurality of fin structures;

oxidizing the first epitaxial semiconductor material; and

forming a second epitaxial semiconductor material on said second of said first and second plurality of fin structures.

17. The method of claim 16, wherein said oxidizing the first epitaxial semiconductor material forms an oxide including said germanium that obstructs said second epitaxial semiconductor material from being formed on the first plurality of fin structures in the first device region.

18. The method of claim 17, wherein the first epitaxial semiconductor material is comprised of a p-type conductivity dopant, and the second epitaxial semiconductor material is comprised of an n-type conductivity dopant.

19. A method of forming a fin structure comprising:

forming a dielectric fin liner comprising hafnium and oxygen on at least one of a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region;

forming a gate structure;

depositing a SiOCN layer on the gate structure and over the first and second plurality of fin structures;

etching the SiOCN layer to form a SiOCN dielectric spacer on the channel region of said at least one of the first and second plurality of fin structures;

forming a first epitaxial semiconductor material on one for said first and second plurality of fin structures from which the dielectric fin liner is removed, wherein a remaining portion of the dielectric fin liner remains on a second of said first and second plurality of fin structures;

oxidizing the first epitaxial semiconductor material; and

forming a second epitaxial semiconductor material on said second of said first and second plurality of fin structures.

20. The method of claim 19, wherein the first epitaxial semiconductor material comprises germanium.