Techniques for tiling arrays of pixel elements and fabricating hybridized tiles

• US 9,748,214 B2
• Filed: 10/19/2015
• Issued: 08/29/2017
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Santa Barbara Infrared Inc. (Heico Corporation)
• Original Assignee: Santa Barbara Infrared Inc. (Heico Corporation)
• Inventors: LaVeigne, Joseph Donald
• Primary Examiner(s): TANINGCO, MARCUS H
• Application Number:
  US14/887,294
• Publication Number:
  US 20160104696A1
• Time in Patent Office: 680 Days
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: G01J 2005/106 Arrays
• CPC Class Codes: G01J 2005/202 Arrays
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: G01J 5/024 Special manufacturing steps or sacrificial layers or layer structures
• CPC Class Codes: G01J 5/045 Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements getter arrangements per se H01L23/26 and H01L21/3221
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/14649 Infrared imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 31/186 Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

A first substrate having an array of emitters or detectors may be joined by bump bonding with a second substrate having read-in (RIIC) or read-out (ROIC) circuitry. After the two substrates are joined, the resulting assembly may be singulated to form sub-arrays such as tiles sub-arrays having pixel elements which may be arranged on a routing layer or carrier to form a larger array. Edge features of the tiles may provide for physical alignment, mechanical attachment and chip-to-chip communication. The pixel elements may be thermal emitter elements for IR image projectors, thermal detector elements for microbolometers, LED-based emitters, or quantum photon detectors such as those found in visible, infrared and ultraviolet FPAs (focal plane arrays), and the like.

Claims

1. A large array of hybridized tiles, a given hybridized tile of semiconductor elements and control circuitry comprising:

a first electronic component comprising a plurality of individual semiconductor elements on a first substrate;

a first set of bump contacts disposed on the individual semiconductor elements;

a second electronic component comprising control circuitry on a second substrate for operating the semiconductor elements; and

a second set of bump contacts on the second substrate;

wherein;

the first and second substrates are joined, face-to-face, and the first set of bump contacts is connected with the second set of bump contacts, resulting in a hybridized tile of semiconductor elements and control circuitry extending over an area which is smaller than an overall surface area of the first and second substrates and which is singulated from the first and second substrates;

further comprising;

back surface connections on each of a plurality of hybridized tiles;

the plurality of hybridized tiles are mounted on a routing layer having front surface connections; and

the back surface connections of the hybridized tiles are connected to the front surface connections of the routing layer.

2. The large array of hybridized tiles of claim 1, wherein:

the semiconductor elements comprise emitters or detectors; and

the control circuitry comprises read in circuitry (RIIC) or read out circuitry (ROTC).

3. The large array of hybridized tiles of claim 1, further comprising:

the alignment features extend from edges of the hybridized tile for facilitating tiling a plurality of hybridized tiles into the large array.

4. The large array of hybridized tiles of claim 3, wherein:

physical alignment features are provided on side edges of the hybridized tiles; and

the physical alignment features on a side edge of a given tile are capable of mating with the physical alignment features on a side edge of an adjacent tile in the large array of tiles.

5. The large array of hybridized tiles of claim 4, wherein:

the physical alignment features comprise bump features protruding from side edges of the tiles and corresponding recess features extending into side edges of the tiles.

6. The large array of hybridized tiles of claim 1, further comprising:

electrical connection features disposed on at least some side edges of the tile;

wherein the electrical connection features on a side edge of the tile connect with electrical connection features on a side edge of an adjacent tile in the large array of tiles.

7. The large array of hybridized tiles of claim 1, wherein:

the first and second substrates comprise semiconductor wafers.

8. A method of making a hybridized array of semiconductor elements and control circuitry comprising:

providing a plurality of individual semiconductor elements on a first substrate;

providing a first set of bump contacts on the individual semiconductor elements;

providing control circuitry on a second substrate for operating the semiconductor elements;

providing a second set of bump contacts on the second substrate;

joining the first and second substrates, face-to-face, and connecting the first set of bump contacts with the second set of bump contacts; and

after joining the first and second substrates, singulating a resulting hybridized array of semiconductor elements and control circuitry from the first and second substrates;

further comprising;

providing back surface connections on each of a plurality of hybridized arrays;

mounting the plurality of hybridized arrays on a routing layer having front surface connections; and

connecting the back surface connections to the front surface connections using through chip routing techniques wherein vias are disposed below the pixel elements.

9. The method of claim 8, further comprising:

mounting the hybridized arrays with a sub-pixel size to zero gap at seams between adjacent hybridized arrays.

10. The method of claim 8, wherein:

the semiconductor elements comprise radiating or detecting elements.

11. The method of claim 8, wherein:

the semiconductor elements comprise emitters or detectors; and

the control circuitry comprises read in circuitry (RIIC) or read out circuitry (ROTC).

12. The method of claim 8, further comprising:

providing physical alignment features on side edges of the hybridized arrays;

wherein the physical alignment features on a side edge of a given hybridized array are capable of mating with the physical alignment features on a side edge of an adjacent hybridized array in an array of hybridized arrays.

13. The method of claim 12, wherein:

the physical alignment features comprise bump features protruding from side edges of the hybridized arrays and corresponding recess features extending into side edges of the hybridized arrays.

14. The method of claim 13, wherein:

singulating comprises removing an outer area of the first and second substrates, and

singulating reveals the physical alignment features.

15. The method of claim 8, wherein:

the first and second substrates comprise semiconductor wafers.