Semiconductor device and method for fabricating the same

• US 9,748,233 B2
• Filed: 10/02/2015
• Issued: 08/29/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chia Chang, Lin, Chun-Hsien
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US14/873,223
• Publication Number:
  US 20170062416A1
• Time in Patent Office: 697 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76853 characterized by particular after-treatment steps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Claims

1. A semiconductor device, containing:

a substrate;

a first gate structure on the substrate;

a first spacer adjacent to the first gate structure;

a first contact plug adjacent to the first gate structure and contact the first spacer directly; and

a silicon layer around the first gate structure, wherein the first contact plug and the silicon layer comprise different material.

2. The semiconductor device of claim 1, wherein the silicon layer comprises an amorphous silicon layer.

3. The semiconductor device of claim 1, further comprising:

a second gate structure on the substrate;

a second spacer adjacent to the second gate structure;

the silicon layer around the second gate structure; and

the first contact plug between the first gate structure and the second gate structure, wherein the first contact plug contacts the first spacer and the second spacer.

4. The semiconductor device of claim 3, wherein the top surfaces of the silicon layer, the first gate structure, the second gate structure, and the first contact plug are coplanar.

5. The semiconductor device of claim 3, further comprising:

an interlayer dielectric (ILD) layer on the silicon layer, the first gate structure, and the second gate structure; and

a plurality of second contact plugs in the ILD layer and electrically connected to the first gate structure, the second gate structure, and the first contact plug.

6. The semiconductor device of claim 1, wherein the top surfaces of the first contact plug and the first gate structure are coplanar.