Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 9,748,329 B2
• Filed: 03/26/2015
• Issued: 08/29/2017
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok
• Primary Examiner(s): Li, Meiya
• Application Number:
  US14/670,139
• Publication Number:
  US 20150206937A1
• Time in Patent Office: 887 Days
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a first trench extending in a semiconductor region, the first trench having a shield electrode and a gate electrode vertically stacked therein, the shield electrode being insulated from the gate electrode;

a source pad configured to receive a first external connection and electrically coupled to the shield electrode of the first trench;

a gate pad disposed above the semiconductor region and configured to receive a second external connection;

an electrical trace electrically coupled to the gate pad or to the source pad;

a second trench extending in the semiconductor region and disposed directly under at least one of the gate pad and the electrical trace, the second trench having a first electrode disposed therein, the second trench being insulated from the electrical trace by a dielectric when directly under the electrical trace;

a first mesa of semiconductor material adjacent the first trench; and

a second mesa of the semiconductor material adjacent the second trench.

2. The semiconductor device of claim 1, further comprising:

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa, the well region being electrically floating or is electrically coupled to the source pad.

3. The semiconductor device of claim 1, further comprising:

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa, at least one of the well region and the first electrode of the second trench being electrically coupled to the source pad.

4. The semiconductor device of claim 1, wherein the gate electrode is a first gate electrode, the second trench includes a second gate electrode vertically stacked over and insulated from the first electrode, the second gate electrode is electrically coupled to the gate pad.

5. The semiconductor device of claim 4, further comprising:

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa, the well region being electrically coupled to the source pad or is electrically floating.

6. The semiconductor device of claim 1, further comprising:

a third trench extending in a semiconductor region and disposed under the at least one of the gate pad and the electrical trace, the third trench including a gate electrode vertically stacked over and electrically insulated from a shield electrode, the gate electrode being electrically coupled to the gate pad.

7. The semiconductor device of claim 6, further comprising:

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa, the well region being electrically coupled to the source pad or electrically floating.

8. The semiconductor device of claim 1, wherein the first electrode is electrically coupled to the source pad,

the semiconductor device further comprising:

a third trench extending in a semiconductor region and disposed under the at least one of the gate pad and the electrical trace, the third trench including a second electrode that is electrically floating.

9. The semiconductor device of claim 8, further comprising:

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa, the well region being electrically coupled to the source pad or electrically floating.

10. The semiconductor device of claim 1, wherein the second mesa has a width that is equal to or less than 1.25 times a width of the first mesa.

11. The semiconductor device of claim 10, wherein the first electrode is electrically coupled to the source pad.

12. The semiconductor device of claim 1, wherein the electrical trace is electrically coupled to the first trench.

13. The semiconductor device of claim 1, wherein the first electrode is electrically coupled to the source pad, the second mesa has a width that is equal to or less than 1.25 times a width of the first mesa.

14. The semiconductor device of claim 1, wherein the first electrode is electrically floating, the second mesa has a width that is equal to or less than 1.25 times a width of the first mesa.

15. The semiconductor device of claim 1, further comprising:

a shield runner made of a metal and disposed above the semiconductor region and having a portion contacting a top surface of the first electrode, the top surface of the first electrode being at or below a top surface of the semiconductor region.

16. The semiconductor device of claim 15, further comprising:

a third trench including a floating electrode or including an electrode electrically coupled to the source pad.

17. A semiconductor device comprising:

a first trench extending in a semiconductor region, the first trench having a shield electrode and a gate electrode vertically stacked therein, the shield electrode being insulated from the gate electrode;

a source pad configured to receive a first external connection and electrically coupled to the shield electrode of the first trench;

a gate pad disposed above the semiconductor region and configured to receive a second external connection;

an electrical trace electrically coupled to the gate; and

a second trench extending in a semiconductor region and disposed directly under at least one of the gate pad and the electrical trace, the second trench having a first electrode disposed therein, the second trench being insulated from the electrical trace by a dielectric when directly under the electrical trace.

18. The semiconductor device of claim 17, further comprising:

a well region of a first conductivity type disposed in the semiconductor region and adjacent the second trench, the well region being electrically floating or is electrically coupled to the source pad.

19. The semiconductor device of claim 17, further comprising:

a well region of a first conductivity type disposed in the semiconductor region and adjacent the second trench, at least one of the well region and the first electrode of the second trench being electrically coupled to the source pad.

20. The semiconductor device of claim 17, wherein the first electrode is electrically coupled to the source pad or electrically floating.

21. The semiconductor device of claim 17, further comprising:

a mesa adjacent to the second trench, the mesa being a floating p-type mesa region.

22. The semiconductor device of claim 21, wherein the mesa is a first mesa,

the semiconductor device further comprising:

a second mesa adjacent the first trench, the first mesa having a width that is equal to or less than 1.25 times a width of the second mesa.