Semiconductor device having self-isolating bulk substrate and method therefor

• US 9,748,330 B2
• Filed: 04/27/2016
• Issued: 08/29/2017
• Est. Priority Date: 01/11/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Janssens, Johan Camiel Julia
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US15/140,152
• Publication Number:
  US 20170200785A1
• Time in Patent Office: 489 Days
• Field of Search: 257337
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

In one embodiment, a semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Dielectric isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent dielectric isolation regions.

Claims

1. A semiconductor device structure comprising:

a self-isolating bulk semiconductor substrate having first and second opposing major surfaces, wherein the self-isolating bulk semiconductor substrate includes;

a floating buried doped region of a first conductivity type;

a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface,

wherein the doped region abuts the floating buried doped region; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;

a trench isolation region extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein the floating buried doped region abuts the trench isolation region; and

a semiconductor device disposed within the doped region.

2. The structure of claim 1, wherein the doped region and the semiconductor region are provided absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region.

3. The structure of claim 2, wherein the self-isolating bulk semiconductor substrate is provided absent any laterally extending buried oxides or SOI structures that partially or completely vertically separate the doped region from the semiconductor region.

4. The structure of claim 1, wherein the floating buried doped region has a varying dopant concentration.

5. The structure of claim 4, wherein the floating buried region comprises:

a first region adjoining the doped region; and

a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region.

6. The structure of claim 5, wherein the floating buried doped region further comprises a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.

7. The structure of claim 1, wherein the semiconductor device comprises a power MOS device.

8. The structure of claim 1 further comprising a shielding structure disposed within the doped region laterally and vertically enclosing the semiconductor device.

9. The structure of claim 8, wherein the shielding structure comprises:

a buried layer portion of the first conductivity type disposed between the floating buried doped region and the semiconductor device; and

a sinker portion of the first conductivity type laterally disposed between the trench isolation region and the semiconductor device, wherein the sinker portion physically contacts the buried layer portion of the shielding structure, and wherein the semiconductor device comprises a CMOS device.

10. The structure of claim 1, wherein the semiconductor device comprises at least one second doped region of the first conductivity type extending from the first major surface into the doped region and vertically separated from the floating buried doped region by the doped region.

11. A semiconductor device structure comprising:

a bulk semiconductor substrate having first and second opposing major surfaces, wherein the bulk semiconductor substrate comprises;

a floating buried doped region of a first conductivity type;

a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface, and

wherein the doped region abuts the floating buried doped region; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface, wherein the doped region and the semiconductor region are provided absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region;

a pair of laterally separated isolation trenches extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, and wherein the floating buried doped region abuts the pair of laterally separated isolation trenches; and

a semiconductor device disposed within the doped region between the least one pair of laterally separated isolation trenches.

12. The structure of claim 11, wherein the bulk semiconductor substrate is provided absent any laterally extending buried oxides or SOI structures that partially or completely vertically separate the doped region from the semiconductor region.

13. The structure of claim 11, wherein the floating buried doped region comprises:

a first region adjoining the doped region;

a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and

a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.

14. The structure of claim 11 further comprising a shielding structure disposed within the doped region laterally and vertically enclosing the semiconductor device, wherein the shielding structure comprises:

a buried layer portion of the first conductivity type disposed between the floating buried doped region and the semiconductor device; and

a sinker portion of the first conductivity type laterally disposed between the trench isolation region and the semiconductor device, wherein the sinker portion physically contacts the buried layer portion of the shielding structure.

15. The structure of claim 14, wherein the semiconductor device comprises a CMOS device.

16. A semiconductor device structure comprising:

a self-isolating bulk semiconductor substrate having first and second opposing major surfaces, wherein the self-isolating bulk semiconductor substrate comprises;

a floating buried doped region of a first conductivity type;

a doped region of a second conductivity type opposite to the first conductivity type disposed between the floating buried doped region and the first major surface; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface, wherein the doped region and the semiconductor region are provided absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region, and wherein the doped region adjoins the floating buried doped region;

a trench isolation structure extending from the first major surface through the doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein the trench isolation structure comprises a plurality of trench isolation portions in cross-sectional view, and wherein the floating buried doped region abuts each trench isolation portion, and wherein the trench isolation structure defines a plurality of device active regions within the doped region; and

a plurality of semiconductor devices disposed within the device active regions.

17. The structure of claim 16, wherein the self-isolating bulk semiconductor substrate is provided absent any laterally extending buried oxides or SOI structures that partially or completely vertically separate the doped region from the semiconductor region.

18. The structure of claim 16, wherein the floating buried doped region comprises:

a first region adjoining the doped region;

a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and

a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.

19. The structure of claim 16 further comprising a shielding structure disposed within a first device active region laterally and vertically enclosing a first semiconductor device, wherein the shielding structure comprises:

a buried layer portion of the first conductivity type disposed between the floating buried doped region and the first semiconductor device; and

a sinker portion of the first conductivity type laterally disposed between the trench isolation structure and the first semiconductor device, wherein the sinker portion physically contacts the buried layer portion of the shielding structure.

20. The structure of claim 19, wherein:

the first semiconductor device comprises a CMOS device; and

the plurality of semiconductor devices comprises at least one power transistor device disposed in a second device active region.