Gate with self-aligned ledged for enhancement mode GaN transistors

• US 9,748,347 B2
• Filed: 07/30/2014
• Issued: 08/29/2017
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Cao, Jianjun, Lidow, Alexander, Nakata, Alana
• Primary Examiner(s): Niesz, Jamie C
• Application Number:
  US14/447,069
• Publication Number:
  US 20160035847A1
• Time in Patent Office: 1,126 Days
• Field of Search: 257194
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.

Claims

1. A method for manufacturing an enhancement-mode GaN transistor, the method comprising:

forming a GaN layer;

forming a barrier layer on the GaN layer;

depositing source and drain contacts on the barrier layer;

depositing a p-type gate material on the barrier layer;

depositing a gate metal on the p-type gate material;

forming a photoresist over the gate metal;

etching the gate metal and the p-type gate material, wherein the step of etching the p-type gate material comprises forming side surfaces of the p-type gate material that extend horizontally towards the source and drain contacts, respectively, and contact the barrier layer; and

etching the gate metal to form a pair of ledges on the p-type gate material below the gate metal.

2. The method according to claim 1, wherein the step of etching the gate metal comprises etching the gate metal to reduce a width of the gate metal, such that the width of the gate metal is less than a width of the p-type gate material.

3. The method according to claim 1, wherein the pair of ledges of the p-type gate material are self-aligned.